mirror of
https://github.com/u-boot/u-boot.git
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d9b94f28a4
Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
226 lines
6.1 KiB
Plaintext
226 lines
6.1 KiB
Plaintext
Motorola MPC85xxCDS boards
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--------------------------
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The CDS family of boards consists of a PCI backplane called the
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"Arcadia", a PCI-form-factor carrier card that plugs into a PCI slot,
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and a CPU daughter card that bolts onto the daughter card.
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Much of the content of the README.mpc85xxads for the 85xx ADS boards
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applies to the 85xx CDS boards as well. In particular the toolchain,
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the switch nomenclature, and the basis for the memory map. There are
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some differences, though.
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Building U-Boot
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---------------
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The Binutils in current ELDK toolchain will not support MPC85xx
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chip. You need to use binutils-2.14.tar.bz2 (or newer) from
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http://ftp.gnu.org/gnu/binutils.
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The 85xx CDS code base is known to compile using:
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gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)
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Memory Map
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----------
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The memory map for u-boot and linux has been extended w.r.t. the ADS
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platform to allow for utilization of all 85xx CDS devices. The memory
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map is setup for linux to operate properly. The linux source when
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configured for MPC85xx CDS has been updated to reflect the new memory
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map.
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The mapping is:
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0x0000_0000 0x7fff_ffff DDR 2G
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0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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0xa000_0000 0xbfff_ffff PCI2 MEM 512M
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0xe000_0000 0xe00f_ffff CCSR 1M
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0xe200_0000 0xe2ff_ffff PCI1 IO 16M
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0xe300_0000 0xe3ff_ffff PCI2 IO 16M
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0xf000_0000 0xf7ff_ffff SDRAM 128M
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0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
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0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
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0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
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(*) The system control registers (CADMUS) start at offset 0xfdb0_4000
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within the NVRAM/CADMUS region of memory.
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Using Flash
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-----------
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The CDS board has two flash banks, each 8MB in size (2^23 = 0x00800000).
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There is a switch which allows the boot-bank to be selected. The switch
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settings for updating flash are given below.
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The u-boot commands for copying the boot-bank into the secondary bank are
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as follows:
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erase ff780000 ff7fffff
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cp.b fff80000 ff780000 80000
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U-boot/kermit commands for downloading an image, then copying
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it into the secondary bank:
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loadb
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[Drop to kermit:
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^\c
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send <u-boot-bin-image>
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c
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]
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erase ff780000 ff7fffff
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cp.b $loadaddr ff780000 80000
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U-boot commands for downloading an image via tftp and flashing
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it into the second bank:
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tftp 10000 <u-boot.bin.image>
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erase ff780000 ff7fffff
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cp.b 10000 ff780000 80000
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After copying the image into the second bank of flash, be sure to toggle
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SW2[2] on the carrier card before resetting the board in order to set the
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secondary bank as the boot-bank.
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Carrier Board Switches
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----------------------
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As a reminder, you should read the README.mpc85xxads too.
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Most switches on the carrier board should not be changed. The only
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user-settable switches on the carrier board are used to configure
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the flash banks and determining the PCI slot.
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The first two bits of SW2 control how flash is used on the board:
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12345678
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--------
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SW2=00XXXXXX FLASH: Boot bank 1, bank 2 available.
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01XXXXXX FLASH: Boot bank 2, bank 1 available (swapped).
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10XXXXXX FLASH: Boot promjet, bank 1 available
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11XXXXXX FLASH: Boot promjet, bank 2 available
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The boot bank is always mapped to FF80_0000 and listed first by
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the "flinfo" command. The secondary bank is always FF00_0000.
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When using PCI, linux needs to know to which slot the CDS carrier is
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connected.. By convention, the user-specific bits of SW2 are used to
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convey this information:
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12345678
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--------
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SW2=xxxxxx00 PCI SLOT INFORM: The CDS carrier is in slot0 of the Arcadia
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xxxxxx01 PCI SLOT INFORM: The CDS carrier is in slot1 of the Arcadia
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xxxxxx10 PCI SLOT INFORM: The CDS carrier is in slot2 of the Arcadia
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xxxxxx11 PCI SLOT INFORM: The CDS carrier is in slot3 of the Arcadia
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These are cleverly, er, clearly silkscreened as Slot 1 through 4,
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respectively, on the Arcadia near the support posts.
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The default setting of all switches on the carrier board is:
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12345678
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--------
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SW1=01101100
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SW2=0x1111yy x=Flash bank, yy=PCI slot
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SW3=11101111
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SW4=10001000
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8555/41 CPU Card Switches
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-------------------------
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Most switches on the CPU Card should not be changed. However, the
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frequency can be changed by setting SW3:
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12345678
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--------
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SW3=XX00XXXX == CORE:CCB 2:1
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XX01XXXX == CORE:CCB 5:2
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XX10XXXX == CORE:CCB 3:1
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XX11XXXX == CORE:CCB 7:2
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XXXX1000 == CCB:SYSCLK 8:1
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XXXX1010 == CCB:SYSCLK 10:1
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A safe default setting for all switches on the CPU board is:
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12345678
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--------
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SW1=10001111
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SW2=01000111
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SW3=00001000
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SW4=11111110
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8548 CPU Card Switches
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----------------------
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And, just to be confusing, in this set of switches:
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ON = 1
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OFF = 0
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Default
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SW1=11111101
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SW2=10011111
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SW3=11001000 (8X) (2:1)
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SW4=11110011
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SW3=X000XXXX == CORE:CCB 4:1
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X001XXXX == CORE:CCB 9:2
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X010XXXX == CORE:CCB 1:1
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X011XXXX == CORE:CCB 3:2
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X100XXXX == CORE:CCB 2:1
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X101XXXX == CORE:CCB 5:2
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X110XXXX == CORE:CCB 3:1
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X111XXXX == CORE:CCB 7:2
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XXXX0000 == CCB:SYSCLK 16:1
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XXXX0001 == RESERVED
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XXXX0010 == CCB:SYSCLK 2:1
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XXXX0011 == CCB:SYSCLK 3:1
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XXXX0100 == CCB:SYSCLK 4:1
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XXXX0101 == CCB:SYSCLK 5:1
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XXXX0110 == CCB:SYSCLK 6:1
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XXXX0111 == RESERVED
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XXXX1000 == CCB:SYSCLK 8:1
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XXXX1001 == CCB:SYSCLK 9:1
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XXXX1010 == CCB:SYSCLK 10:1
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XXXX1011 == RESERVED
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XXXX1100 == CCB:SYSCLK 12:1
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XXXX1101 == CCB:SYSCLK 20:1
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XXXX1110 == RESERVED
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XXXX1111 == RESERVED
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eDINK Info
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----------
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One bank of flash may contain an eDINK image.
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Memory Map:
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CCSRBAR @ 0xe0000000
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Flash Bank 1 @ 0xfe000000
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Flash Bank 2 @ 0xff000000
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Ram @ 0
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Commands for downloading a u-boot image to memory from edink:
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env -c
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time -s 4/8/2004 4:30p
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dl -k -b -o 100000
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[Drop to kermit:
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^\c
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transmit /binary <u-boot-bin-image>
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c
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]
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fu -l 100000 fe780000 80000
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