mirror of
https://github.com/u-boot/u-boot.git
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53677ef18e
This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
1330 lines
32 KiB
C
1330 lines
32 KiB
C
/*
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* (C) Copyright 2001
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* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* I2C Functions similar to the standard memory functions.
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*
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* There are several parameters in many of the commands that bear further
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* explanations:
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*
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* Two of the commands (imm and imw) take a byte/word/long modifier
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* (e.g. imm.w specifies the word-length modifier). This was done to
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* allow manipulating word-length registers. It was not done on any other
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* commands because it was not deemed useful.
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*
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* {i2c_chip} is the I2C chip address (the first byte sent on the bus).
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* Each I2C chip on the bus has a unique address. On the I2C data bus,
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* the address is the upper seven bits and the LSB is the "read/write"
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* bit. Note that the {i2c_chip} address specified on the command
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* line is not shifted up: e.g. a typical EEPROM memory chip may have
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* an I2C address of 0x50, but the data put on the bus will be 0xA0
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* for write and 0xA1 for read. This "non shifted" address notation
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* matches at least half of the data sheets :-/.
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*
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* {addr} is the address (or offset) within the chip. Small memory
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* chips have 8 bit addresses. Large memory chips have 16 bit
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* addresses. Other memory chips have 9, 10, or 11 bit addresses.
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* Many non-memory chips have multiple registers and {addr} is used
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* as the register index. Some non-memory chips have only one register
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* and therefore don't need any {addr} parameter.
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*
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* The default {addr} parameter is one byte (.1) which works well for
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* memories and registers with 8 bits of address space.
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*
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* You can specify the length of the {addr} field with the optional .0,
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* .1, or .2 modifier (similar to the .b, .w, .l modifier). If you are
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* manipulating a single register device which doesn't use an address
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* field, use "0.0" for the address and the ".0" length field will
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* suppress the address in the I2C data stream. This also works for
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* successive reads using the I2C auto-incrementing memory pointer.
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*
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* If you are manipulating a large memory with 2-byte addresses, use
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* the .2 address modifier, e.g. 210.2 addresses location 528 (decimal).
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*
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* Then there are the unfortunate memory chips that spill the most
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* significant 1, 2, or 3 bits of address into the chip address byte.
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* This effectively makes one chip (logically) look like 2, 4, or
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* 8 chips. This is handled (awkwardly) by #defining
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* CFG_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
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* {addr} field (since .1 is the default, it doesn't actually have to
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* be specified). Examples: given a memory chip at I2C chip address
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* 0x50, the following would happen...
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* imd 50 0 10 display 16 bytes starting at 0x000
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* On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
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* imd 50 100 10 display 16 bytes starting at 0x100
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* On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
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* imd 50 210 10 display 16 bytes starting at 0x210
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* On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
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* This is awfully ugly. It would be nice if someone would think up
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* a better way of handling this.
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*
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* Adapted from cmd_mem.c which is copyright Wolfgang Denk (wd@denx.de).
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*/
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#include <common.h>
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#include <command.h>
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#include <i2c.h>
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#include <asm/byteorder.h>
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/* Display values from last command.
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* Memory modify remembered values are different from display memory.
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*/
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static uchar i2c_dp_last_chip;
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static uint i2c_dp_last_addr;
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static uint i2c_dp_last_alen;
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static uint i2c_dp_last_length = 0x10;
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static uchar i2c_mm_last_chip;
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static uint i2c_mm_last_addr;
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static uint i2c_mm_last_alen;
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/* If only one I2C bus is present, the list of devices to ignore when
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* the probe command is issued is represented by a 1D array of addresses.
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* When multiple buses are present, the list is an array of bus-address
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* pairs. The following macros take care of this */
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#if defined(CFG_I2C_NOPROBES)
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#if defined(CONFIG_I2C_MULTI_BUS)
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static struct
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{
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uchar bus;
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uchar addr;
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} i2c_no_probes[] = CFG_I2C_NOPROBES;
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#define GET_BUS_NUM i2c_get_bus_num()
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#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
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#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
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#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
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#else /* single bus */
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static uchar i2c_no_probes[] = CFG_I2C_NOPROBES;
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#define GET_BUS_NUM 0
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#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
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#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
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#define NO_PROBE_ADDR(i) i2c_no_probes[(i)]
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#endif /* CONFIG_MULTI_BUS */
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#define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
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#endif
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static int
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mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]);
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extern int cmd_get_data_size(char* arg, int default_size);
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/*
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* Syntax:
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* imd {i2c_chip} {addr}{.0, .1, .2} {len}
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*/
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#define DISP_LINE_LEN 16
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int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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u_char chip;
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uint addr, alen, length;
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int j, nbytes, linebytes;
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/* We use the last specified parameters, unless new ones are
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* entered.
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*/
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chip = i2c_dp_last_chip;
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addr = i2c_dp_last_addr;
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alen = i2c_dp_last_alen;
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length = i2c_dp_last_length;
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if (argc < 3) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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if ((flag & CMD_FLAG_REPEAT) == 0) {
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/*
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* New command specified.
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*/
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alen = 1;
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/*
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* I2C chip address
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*/
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chip = simple_strtoul(argv[1], NULL, 16);
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/*
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* I2C data address within the chip. This can be 1 or
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* 2 bytes long. Some day it might be 3 bytes long :-).
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*/
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addr = simple_strtoul(argv[2], NULL, 16);
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alen = 1;
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for (j = 0; j < 8; j++) {
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if (argv[2][j] == '.') {
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alen = argv[2][j+1] - '0';
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if (alen > 4) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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break;
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} else if (argv[2][j] == '\0')
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break;
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}
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/*
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* If another parameter, it is the length to display.
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* Length is the number of objects, not number of bytes.
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*/
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if (argc > 3)
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length = simple_strtoul(argv[3], NULL, 16);
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}
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/*
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* Print the lines.
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*
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* We buffer all read data, so we can make sure data is read only
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* once.
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*/
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nbytes = length;
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do {
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unsigned char linebuf[DISP_LINE_LEN];
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unsigned char *cp;
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linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
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if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
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puts ("Error reading the chip.\n");
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else {
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printf("%04x:", addr);
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cp = linebuf;
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for (j=0; j<linebytes; j++) {
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printf(" %02x", *cp++);
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addr++;
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}
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puts (" ");
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cp = linebuf;
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for (j=0; j<linebytes; j++) {
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if ((*cp < 0x20) || (*cp > 0x7e))
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puts (".");
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else
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printf("%c", *cp);
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cp++;
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}
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putc ('\n');
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}
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nbytes -= linebytes;
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} while (nbytes > 0);
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i2c_dp_last_chip = chip;
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i2c_dp_last_addr = addr;
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i2c_dp_last_alen = alen;
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i2c_dp_last_length = length;
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return 0;
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}
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int do_i2c_mm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
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}
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int do_i2c_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
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}
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/* Write (fill) memory
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*
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* Syntax:
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* imw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
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*/
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int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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uchar chip;
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ulong addr;
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uint alen;
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uchar byte;
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int count;
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int j;
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if ((argc < 4) || (argc > 5)) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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/*
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* Chip is always specified.
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*/
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chip = simple_strtoul(argv[1], NULL, 16);
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/*
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* Address is always specified.
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*/
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addr = simple_strtoul(argv[2], NULL, 16);
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alen = 1;
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for (j = 0; j < 8; j++) {
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if (argv[2][j] == '.') {
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alen = argv[2][j+1] - '0';
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if (alen > 4) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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break;
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} else if (argv[2][j] == '\0')
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break;
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}
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/*
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* Value to write is always specified.
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*/
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byte = simple_strtoul(argv[3], NULL, 16);
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/*
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* Optional count
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*/
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if (argc == 5)
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count = simple_strtoul(argv[4], NULL, 16);
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else
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count = 1;
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while (count-- > 0) {
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if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
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puts ("Error writing the chip.\n");
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/*
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* Wait for the write to complete. The write can take
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* up to 10mSec (we allow a little more time).
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*
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* On some chips, while the write is in progress, the
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* chip doesn't respond. This apparently isn't a
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* universal feature so we don't take advantage of it.
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*/
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/*
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* No write delay with FRAM devices.
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*/
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#if !defined(CFG_I2C_FRAM)
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udelay(11000);
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#endif
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#if 0
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for (timeout = 0; timeout < 10; timeout++) {
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udelay(2000);
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if (i2c_probe(chip) == 0)
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break;
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}
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#endif
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}
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return (0);
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}
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/* Calculate a CRC on memory
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*
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* Syntax:
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* icrc32 {i2c_chip} {addr}{.0, .1, .2} {count}
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*/
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int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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uchar chip;
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ulong addr;
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uint alen;
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int count;
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uchar byte;
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ulong crc;
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ulong err;
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int j;
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if (argc < 4) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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/*
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* Chip is always specified.
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*/
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chip = simple_strtoul(argv[1], NULL, 16);
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/*
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* Address is always specified.
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*/
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addr = simple_strtoul(argv[2], NULL, 16);
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alen = 1;
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for (j = 0; j < 8; j++) {
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if (argv[2][j] == '.') {
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alen = argv[2][j+1] - '0';
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if (alen > 4) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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break;
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} else if (argv[2][j] == '\0')
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break;
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}
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/*
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* Count is always specified
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*/
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count = simple_strtoul(argv[3], NULL, 16);
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printf ("CRC32 for %08lx ... %08lx ==> ", addr, addr + count - 1);
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/*
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* CRC a byte at a time. This is going to be slooow, but hey, the
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* memories are small and slow too so hopefully nobody notices.
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*/
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crc = 0;
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err = 0;
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while (count-- > 0) {
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if (i2c_read(chip, addr, alen, &byte, 1) != 0)
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err++;
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crc = crc32 (crc, &byte, 1);
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addr++;
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}
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if (err > 0)
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puts ("Error reading the chip,\n");
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else
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printf ("%08lx\n", crc);
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return 0;
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}
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/* Modify memory.
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*
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* Syntax:
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* imm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
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* inm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
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*/
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static int
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mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
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{
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uchar chip;
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ulong addr;
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uint alen;
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ulong data;
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int size = 1;
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int nbytes;
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int j;
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extern char console_buffer[];
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if (argc != 3) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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#ifdef CONFIG_BOOT_RETRY_TIME
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reset_cmd_timeout(); /* got a good command to get here */
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#endif
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/*
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* We use the last specified parameters, unless new ones are
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* entered.
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*/
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chip = i2c_mm_last_chip;
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addr = i2c_mm_last_addr;
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alen = i2c_mm_last_alen;
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if ((flag & CMD_FLAG_REPEAT) == 0) {
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/*
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* New command specified. Check for a size specification.
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* Defaults to byte if no or incorrect specification.
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*/
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size = cmd_get_data_size(argv[0], 1);
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/*
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* Chip is always specified.
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*/
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chip = simple_strtoul(argv[1], NULL, 16);
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/*
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* Address is always specified.
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*/
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addr = simple_strtoul(argv[2], NULL, 16);
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alen = 1;
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for (j = 0; j < 8; j++) {
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if (argv[2][j] == '.') {
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alen = argv[2][j+1] - '0';
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if (alen > 4) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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break;
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} else if (argv[2][j] == '\0')
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break;
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}
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}
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/*
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* Print the address, followed by value. Then accept input for
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* the next value. A non-converted value exits.
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*/
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do {
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printf("%08lx:", addr);
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if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
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puts ("\nError reading the chip,\n");
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else {
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data = cpu_to_be32(data);
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if (size == 1)
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printf(" %02lx", (data >> 24) & 0x000000FF);
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else if (size == 2)
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printf(" %04lx", (data >> 16) & 0x0000FFFF);
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else
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printf(" %08lx", data);
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}
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nbytes = readline (" ? ");
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if (nbytes == 0) {
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/*
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* <CR> pressed as only input, don't modify current
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* location and move to next.
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*/
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if (incrflag)
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addr += size;
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nbytes = size;
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#ifdef CONFIG_BOOT_RETRY_TIME
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reset_cmd_timeout(); /* good enough to not time out */
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#endif
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}
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#ifdef CONFIG_BOOT_RETRY_TIME
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else if (nbytes == -2)
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break; /* timed out, exit the command */
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#endif
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else {
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char *endp;
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data = simple_strtoul(console_buffer, &endp, 16);
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if (size == 1)
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data = data << 24;
|
|
else if (size == 2)
|
|
data = data << 16;
|
|
data = be32_to_cpu(data);
|
|
nbytes = endp - console_buffer;
|
|
if (nbytes) {
|
|
#ifdef CONFIG_BOOT_RETRY_TIME
|
|
/*
|
|
* good enough to not time out
|
|
*/
|
|
reset_cmd_timeout();
|
|
#endif
|
|
if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
|
|
puts ("Error writing the chip.\n");
|
|
#ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS
|
|
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
|
|
#endif
|
|
if (incrflag)
|
|
addr += size;
|
|
}
|
|
}
|
|
} while (nbytes);
|
|
|
|
chip = i2c_mm_last_chip;
|
|
addr = i2c_mm_last_addr;
|
|
alen = i2c_mm_last_alen;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Syntax:
|
|
* iprobe {addr}{.0, .1, .2}
|
|
*/
|
|
int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|
{
|
|
int j;
|
|
#if defined(CFG_I2C_NOPROBES)
|
|
int k, skip;
|
|
uchar bus = GET_BUS_NUM;
|
|
#endif /* NOPROBES */
|
|
|
|
puts ("Valid chip addresses:");
|
|
for (j = 0; j < 128; j++) {
|
|
#if defined(CFG_I2C_NOPROBES)
|
|
skip = 0;
|
|
for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
|
|
if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
|
|
skip = 1;
|
|
break;
|
|
}
|
|
}
|
|
if (skip)
|
|
continue;
|
|
#endif
|
|
if (i2c_probe(j) == 0)
|
|
printf(" %02X", j);
|
|
}
|
|
putc ('\n');
|
|
|
|
#if defined(CFG_I2C_NOPROBES)
|
|
puts ("Excluded chip addresses:");
|
|
for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
|
|
if (COMPARE_BUS(bus,k))
|
|
printf(" %02X", NO_PROBE_ADDR(k));
|
|
}
|
|
putc ('\n');
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Syntax:
|
|
* iloop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
|
|
* {length} - Number of bytes to read
|
|
* {delay} - A DECIMAL number and defaults to 1000 uSec
|
|
*/
|
|
int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|
{
|
|
u_char chip;
|
|
ulong alen;
|
|
uint addr;
|
|
uint length;
|
|
u_char bytes[16];
|
|
int delay;
|
|
int j;
|
|
|
|
if (argc < 3) {
|
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* Chip is always specified.
|
|
*/
|
|
chip = simple_strtoul(argv[1], NULL, 16);
|
|
|
|
/*
|
|
* Address is always specified.
|
|
*/
|
|
addr = simple_strtoul(argv[2], NULL, 16);
|
|
alen = 1;
|
|
for (j = 0; j < 8; j++) {
|
|
if (argv[2][j] == '.') {
|
|
alen = argv[2][j+1] - '0';
|
|
if (alen > 4) {
|
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
|
return 1;
|
|
}
|
|
break;
|
|
} else if (argv[2][j] == '\0')
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Length is the number of objects, not number of bytes.
|
|
*/
|
|
length = 1;
|
|
length = simple_strtoul(argv[3], NULL, 16);
|
|
if (length > sizeof(bytes))
|
|
length = sizeof(bytes);
|
|
|
|
/*
|
|
* The delay time (uSec) is optional.
|
|
*/
|
|
delay = 1000;
|
|
if (argc > 3)
|
|
delay = simple_strtoul(argv[4], NULL, 10);
|
|
/*
|
|
* Run the loop...
|
|
*/
|
|
while (1) {
|
|
if (i2c_read(chip, addr, alen, bytes, length) != 0)
|
|
puts ("Error reading the chip.\n");
|
|
udelay(delay);
|
|
}
|
|
|
|
/* NOTREACHED */
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* The SDRAM command is separately configured because many
|
|
* (most?) embedded boards don't use SDRAM DIMMs.
|
|
*/
|
|
#if defined(CONFIG_CMD_SDRAM)
|
|
static void print_ddr2_tcyc (u_char const b)
|
|
{
|
|
printf ("%d.", (b >> 4) & 0x0F);
|
|
switch (b & 0x0F) {
|
|
case 0x0:
|
|
case 0x1:
|
|
case 0x2:
|
|
case 0x3:
|
|
case 0x4:
|
|
case 0x5:
|
|
case 0x6:
|
|
case 0x7:
|
|
case 0x8:
|
|
case 0x9:
|
|
printf ("%d ns\n", b & 0x0F);
|
|
break;
|
|
case 0xA:
|
|
puts ("25 ns\n");
|
|
break;
|
|
case 0xB:
|
|
puts ("33 ns\n");
|
|
break;
|
|
case 0xC:
|
|
puts ("66 ns\n");
|
|
break;
|
|
case 0xD:
|
|
puts ("75 ns\n");
|
|
break;
|
|
default:
|
|
puts ("?? ns\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void decode_bits (u_char const b, char const *str[], int const do_once)
|
|
{
|
|
u_char mask;
|
|
|
|
for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
|
|
if (b & mask) {
|
|
puts (*str);
|
|
if (do_once)
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Syntax:
|
|
* sdram {i2c_chip}
|
|
*/
|
|
int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
|
{
|
|
enum { unknown, EDO, SDRAM, DDR2 } type;
|
|
|
|
u_char chip;
|
|
u_char data[128];
|
|
u_char cksum;
|
|
int j;
|
|
|
|
static const char *decode_CAS_DDR2[] = {
|
|
" TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
|
|
};
|
|
|
|
static const char *decode_CAS_default[] = {
|
|
" TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
|
|
};
|
|
|
|
static const char *decode_CS_WE_default[] = {
|
|
" TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
|
|
};
|
|
|
|
static const char *decode_byte21_default[] = {
|
|
" TBD (bit 7)\n",
|
|
" Redundant row address\n",
|
|
" Differential clock input\n",
|
|
" Registerd DQMB inputs\n",
|
|
" Buffered DQMB inputs\n",
|
|
" On-card PLL\n",
|
|
" Registered address/control lines\n",
|
|
" Buffered address/control lines\n"
|
|
};
|
|
|
|
static const char *decode_byte22_DDR2[] = {
|
|
" TBD (bit 7)\n",
|
|
" TBD (bit 6)\n",
|
|
" TBD (bit 5)\n",
|
|
" TBD (bit 4)\n",
|
|
" TBD (bit 3)\n",
|
|
" Supports partial array self refresh\n",
|
|
" Supports 50 ohm ODT\n",
|
|
" Supports weak driver\n"
|
|
};
|
|
|
|
static const char *decode_row_density_DDR2[] = {
|
|
"512 MiB", "256 MiB", "128 MiB", "16 GiB",
|
|
"8 GiB", "4 GiB", "2 GiB", "1 GiB"
|
|
};
|
|
|
|
static const char *decode_row_density_default[] = {
|
|
"512 MiB", "256 MiB", "128 MiB", "64 MiB",
|
|
"32 MiB", "16 MiB", "8 MiB", "4 MiB"
|
|
};
|
|
|
|
if (argc < 2) {
|
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
|
return 1;
|
|
}
|
|
/*
|
|
* Chip is always specified.
|
|
*/
|
|
chip = simple_strtoul (argv[1], NULL, 16);
|
|
|
|
if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
|
|
puts ("No SDRAM Serial Presence Detect found.\n");
|
|
return 1;
|
|
}
|
|
|
|
cksum = 0;
|
|
for (j = 0; j < 63; j++) {
|
|
cksum += data[j];
|
|
}
|
|
if (cksum != data[63]) {
|
|
printf ("WARNING: Configuration data checksum failure:\n"
|
|
" is 0x%02x, calculated 0x%02x\n", data[63], cksum);
|
|
}
|
|
printf ("SPD data revision %d.%d\n",
|
|
(data[62] >> 4) & 0x0F, data[62] & 0x0F);
|
|
printf ("Bytes used 0x%02X\n", data[0]);
|
|
printf ("Serial memory size 0x%02X\n", 1 << data[1]);
|
|
|
|
puts ("Memory type ");
|
|
switch (data[2]) {
|
|
case 2:
|
|
type = EDO;
|
|
puts ("EDO\n");
|
|
break;
|
|
case 4:
|
|
type = SDRAM;
|
|
puts ("SDRAM\n");
|
|
break;
|
|
case 8:
|
|
type = DDR2;
|
|
puts ("DDR2\n");
|
|
break;
|
|
default:
|
|
type = unknown;
|
|
puts ("unknown\n");
|
|
break;
|
|
}
|
|
|
|
puts ("Row address bits ");
|
|
if ((data[3] & 0x00F0) == 0)
|
|
printf ("%d\n", data[3] & 0x0F);
|
|
else
|
|
printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
|
|
|
|
puts ("Column address bits ");
|
|
if ((data[4] & 0x00F0) == 0)
|
|
printf ("%d\n", data[4] & 0x0F);
|
|
else
|
|
printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("Number of ranks %d\n",
|
|
(data[5] & 0x07) + 1);
|
|
break;
|
|
default:
|
|
printf ("Module rows %d\n", data[5]);
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("Module data width %d bits\n", data[6]);
|
|
break;
|
|
default:
|
|
printf ("Module data width %d bits\n",
|
|
(data[7] << 8) | data[6]);
|
|
break;
|
|
}
|
|
|
|
puts ("Interface signal levels ");
|
|
switch(data[8]) {
|
|
case 0: puts ("TTL 5.0 V\n"); break;
|
|
case 1: puts ("LVTTL\n"); break;
|
|
case 2: puts ("HSTL 1.5 V\n"); break;
|
|
case 3: puts ("SSTL 3.3 V\n"); break;
|
|
case 4: puts ("SSTL 2.5 V\n"); break;
|
|
case 5: puts ("SSTL 1.8 V\n"); break;
|
|
default: puts ("unknown\n"); break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("SDRAM cycle time ");
|
|
print_ddr2_tcyc (data[9]);
|
|
break;
|
|
default:
|
|
printf ("SDRAM cycle time %d.%d ns\n",
|
|
(data[9] >> 4) & 0x0F, data[9] & 0x0F);
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("SDRAM access time 0.%d%d ns\n",
|
|
(data[10] >> 4) & 0x0F, data[10] & 0x0F);
|
|
break;
|
|
default:
|
|
printf ("SDRAM access time %d.%d ns\n",
|
|
(data[10] >> 4) & 0x0F, data[10] & 0x0F);
|
|
break;
|
|
}
|
|
|
|
puts ("EDC configuration ");
|
|
switch (data[11]) {
|
|
case 0: puts ("None\n"); break;
|
|
case 1: puts ("Parity\n"); break;
|
|
case 2: puts ("ECC\n"); break;
|
|
default: puts ("unknown\n"); break;
|
|
}
|
|
|
|
if ((data[12] & 0x80) == 0)
|
|
puts ("No self refresh, rate ");
|
|
else
|
|
puts ("Self refresh, rate ");
|
|
|
|
switch(data[12] & 0x7F) {
|
|
case 0: puts ("15.625 us\n"); break;
|
|
case 1: puts ("3.9 us\n"); break;
|
|
case 2: puts ("7.8 us\n"); break;
|
|
case 3: puts ("31.3 us\n"); break;
|
|
case 4: puts ("62.5 us\n"); break;
|
|
case 5: puts ("125 us\n"); break;
|
|
default: puts ("unknown\n"); break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("SDRAM width (primary) %d\n", data[13]);
|
|
break;
|
|
default:
|
|
printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
|
|
if ((data[13] & 0x80) != 0) {
|
|
printf (" (second bank) %d\n",
|
|
2 * (data[13] & 0x7F));
|
|
}
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
if (data[14] != 0)
|
|
printf ("EDC width %d\n", data[14]);
|
|
break;
|
|
default:
|
|
if (data[14] != 0) {
|
|
printf ("EDC width %d\n",
|
|
data[14] & 0x7F);
|
|
|
|
if ((data[14] & 0x80) != 0) {
|
|
printf (" (second bank) %d\n",
|
|
2 * (data[14] & 0x7F));
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (DDR2 != type) {
|
|
printf ("Min clock delay, back-to-back random column addresses "
|
|
"%d\n", data[15]);
|
|
}
|
|
|
|
puts ("Burst length(s) ");
|
|
if (data[16] & 0x80) puts (" Page");
|
|
if (data[16] & 0x08) puts (" 8");
|
|
if (data[16] & 0x04) puts (" 4");
|
|
if (data[16] & 0x02) puts (" 2");
|
|
if (data[16] & 0x01) puts (" 1");
|
|
putc ('\n');
|
|
printf ("Number of banks %d\n", data[17]);
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
puts ("CAS latency(s) ");
|
|
decode_bits (data[18], decode_CAS_DDR2, 0);
|
|
putc ('\n');
|
|
break;
|
|
default:
|
|
puts ("CAS latency(s) ");
|
|
decode_bits (data[18], decode_CAS_default, 0);
|
|
putc ('\n');
|
|
break;
|
|
}
|
|
|
|
if (DDR2 != type) {
|
|
puts ("CS latency(s) ");
|
|
decode_bits (data[19], decode_CS_WE_default, 0);
|
|
putc ('\n');
|
|
}
|
|
|
|
if (DDR2 != type) {
|
|
puts ("WE latency(s) ");
|
|
decode_bits (data[20], decode_CS_WE_default, 0);
|
|
putc ('\n');
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
puts ("Module attributes:\n");
|
|
if (data[21] & 0x80)
|
|
puts (" TBD (bit 7)\n");
|
|
if (data[21] & 0x40)
|
|
puts (" Analysis probe installed\n");
|
|
if (data[21] & 0x20)
|
|
puts (" TBD (bit 5)\n");
|
|
if (data[21] & 0x10)
|
|
puts (" FET switch external enable\n");
|
|
printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
|
|
if (data[20] & 0x11) {
|
|
printf (" %d active registers on DIMM\n",
|
|
(data[21] & 0x03) + 1);
|
|
}
|
|
break;
|
|
default:
|
|
puts ("Module attributes:\n");
|
|
if (!data[21])
|
|
puts (" (none)\n");
|
|
else
|
|
decode_bits (data[21], decode_byte21_default, 0);
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
decode_bits (data[22], decode_byte22_DDR2, 0);
|
|
break;
|
|
default:
|
|
puts ("Device attributes:\n");
|
|
if (data[22] & 0x80) puts (" TBD (bit 7)\n");
|
|
if (data[22] & 0x40) puts (" TBD (bit 6)\n");
|
|
if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
|
|
else puts (" Upper Vcc tolerance 10%\n");
|
|
if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
|
|
else puts (" Lower Vcc tolerance 10%\n");
|
|
if (data[22] & 0x08) puts (" Supports write1/read burst\n");
|
|
if (data[22] & 0x04) puts (" Supports precharge all\n");
|
|
if (data[22] & 0x02) puts (" Supports auto precharge\n");
|
|
if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("SDRAM cycle time (2nd highest CAS latency) ");
|
|
print_ddr2_tcyc (data[23]);
|
|
break;
|
|
default:
|
|
printf ("SDRAM cycle time (2nd highest CAS latency) %d."
|
|
"%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("SDRAM access from clock (2nd highest CAS latency) 0."
|
|
"%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
|
|
break;
|
|
default:
|
|
printf ("SDRAM access from clock (2nd highest CAS latency) %d."
|
|
"%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("SDRAM cycle time (3rd highest CAS latency) ");
|
|
print_ddr2_tcyc (data[25]);
|
|
break;
|
|
default:
|
|
printf ("SDRAM cycle time (3rd highest CAS latency) %d."
|
|
"%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("SDRAM access from clock (3rd highest CAS latency) 0."
|
|
"%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
|
|
break;
|
|
default:
|
|
printf ("SDRAM access from clock (3rd highest CAS latency) %d."
|
|
"%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("Minimum row precharge %d.%02d ns\n",
|
|
(data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
|
|
break;
|
|
default:
|
|
printf ("Minimum row precharge %d ns\n", data[27]);
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("Row active to row active min %d.%02d ns\n",
|
|
(data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
|
|
break;
|
|
default:
|
|
printf ("Row active to row active min %d ns\n", data[28]);
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("RAS to CAS delay min %d.%02d ns\n",
|
|
(data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
|
|
break;
|
|
default:
|
|
printf ("RAS to CAS delay min %d ns\n", data[29]);
|
|
break;
|
|
}
|
|
|
|
printf ("Minimum RAS pulse width %d ns\n", data[30]);
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
puts ("Density of each row ");
|
|
decode_bits (data[31], decode_row_density_DDR2, 1);
|
|
putc ('\n');
|
|
break;
|
|
default:
|
|
puts ("Density of each row ");
|
|
decode_bits (data[31], decode_row_density_default, 1);
|
|
putc ('\n');
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
puts ("Command and Address setup ");
|
|
if (data[32] >= 0xA0) {
|
|
printf ("1.%d%d ns\n",
|
|
((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
|
|
} else {
|
|
printf ("0.%d%d ns\n",
|
|
((data[32] >> 4) & 0x0F), data[32] & 0x0F);
|
|
}
|
|
break;
|
|
default:
|
|
printf ("Command and Address setup %c%d.%d ns\n",
|
|
(data[32] & 0x80) ? '-' : '+',
|
|
(data[32] >> 4) & 0x07, data[32] & 0x0F);
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
puts ("Command and Address hold ");
|
|
if (data[33] >= 0xA0) {
|
|
printf ("1.%d%d ns\n",
|
|
((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
|
|
} else {
|
|
printf ("0.%d%d ns\n",
|
|
((data[33] >> 4) & 0x0F), data[33] & 0x0F);
|
|
}
|
|
break;
|
|
default:
|
|
printf ("Command and Address hold %c%d.%d ns\n",
|
|
(data[33] & 0x80) ? '-' : '+',
|
|
(data[33] >> 4) & 0x07, data[33] & 0x0F);
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("Data signal input setup 0.%d%d ns\n",
|
|
(data[34] >> 4) & 0x0F, data[34] & 0x0F);
|
|
break;
|
|
default:
|
|
printf ("Data signal input setup %c%d.%d ns\n",
|
|
(data[34] & 0x80) ? '-' : '+',
|
|
(data[34] >> 4) & 0x07, data[34] & 0x0F);
|
|
break;
|
|
}
|
|
|
|
switch (type) {
|
|
case DDR2:
|
|
printf ("Data signal input hold 0.%d%d ns\n",
|
|
(data[35] >> 4) & 0x0F, data[35] & 0x0F);
|
|
break;
|
|
default:
|
|
printf ("Data signal input hold %c%d.%d ns\n",
|
|
(data[35] & 0x80) ? '-' : '+',
|
|
(data[35] >> 4) & 0x07, data[35] & 0x0F);
|
|
break;
|
|
}
|
|
|
|
puts ("Manufacturer's JEDEC ID ");
|
|
for (j = 64; j <= 71; j++)
|
|
printf ("%02X ", data[j]);
|
|
putc ('\n');
|
|
printf ("Manufacturing Location %02X\n", data[72]);
|
|
puts ("Manufacturer's Part Number ");
|
|
for (j = 73; j <= 90; j++)
|
|
printf ("%02X ", data[j]);
|
|
putc ('\n');
|
|
printf ("Revision Code %02X %02X\n", data[91], data[92]);
|
|
printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
|
|
puts ("Assembly Serial Number ");
|
|
for (j = 95; j <= 98; j++)
|
|
printf ("%02X ", data[j]);
|
|
putc ('\n');
|
|
|
|
if (DDR2 != type) {
|
|
printf ("Speed rating PC%d\n",
|
|
data[126] == 0x66 ? 66 : data[126]);
|
|
}
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_I2C_CMD_TREE)
|
|
#if defined(CONFIG_I2C_MULTI_BUS)
|
|
int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
|
{
|
|
int bus_idx, ret=0;
|
|
|
|
if (argc == 1)
|
|
/* querying current setting */
|
|
printf("Current bus is %d\n", i2c_get_bus_num());
|
|
else {
|
|
bus_idx = simple_strtoul(argv[1], NULL, 10);
|
|
printf("Setting bus to %d\n", bus_idx);
|
|
ret = i2c_set_bus_num(bus_idx);
|
|
if (ret)
|
|
printf("Failure changing bus number (%d)\n", ret);
|
|
}
|
|
return ret;
|
|
}
|
|
#endif /* CONFIG_I2C_MULTI_BUS */
|
|
|
|
int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
|
{
|
|
int speed, ret=0;
|
|
|
|
if (argc == 1)
|
|
/* querying current speed */
|
|
printf("Current bus speed=%d\n", i2c_get_bus_speed());
|
|
else {
|
|
speed = simple_strtoul(argv[1], NULL, 10);
|
|
printf("Setting bus speed to %d Hz\n", speed);
|
|
ret = i2c_set_bus_speed(speed);
|
|
if (ret)
|
|
printf("Failure changing bus speed (%d)\n", ret);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
|
{
|
|
#if defined(CONFIG_I2C_MULTI_BUS)
|
|
if (!strncmp(argv[1], "de", 2))
|
|
return do_i2c_bus_num(cmdtp, flag, --argc, ++argv);
|
|
#endif /* CONFIG_I2C_MULTI_BUS */
|
|
if (!strncmp(argv[1], "sp", 2))
|
|
return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv);
|
|
if (!strncmp(argv[1], "md", 2))
|
|
return do_i2c_md(cmdtp, flag, --argc, ++argv);
|
|
if (!strncmp(argv[1], "mm", 2))
|
|
return do_i2c_mm(cmdtp, flag, --argc, ++argv);
|
|
if (!strncmp(argv[1], "mw", 2))
|
|
return do_i2c_mw(cmdtp, flag, --argc, ++argv);
|
|
if (!strncmp(argv[1], "nm", 2))
|
|
return do_i2c_nm(cmdtp, flag, --argc, ++argv);
|
|
if (!strncmp(argv[1], "cr", 2))
|
|
return do_i2c_crc(cmdtp, flag, --argc, ++argv);
|
|
if (!strncmp(argv[1], "pr", 2))
|
|
return do_i2c_probe(cmdtp, flag, --argc, ++argv);
|
|
if (!strncmp(argv[1], "lo", 2))
|
|
return do_i2c_loop(cmdtp, flag, --argc, ++argv);
|
|
#if defined(CONFIG_CMD_SDRAM)
|
|
if (!strncmp(argv[1], "sd", 2))
|
|
return do_sdram(cmdtp, flag, --argc, ++argv);
|
|
#endif
|
|
else
|
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_I2C_CMD_TREE */
|
|
|
|
/***************************************************/
|
|
|
|
#if defined(CONFIG_I2C_CMD_TREE)
|
|
U_BOOT_CMD(
|
|
i2c, 6, 1, do_i2c,
|
|
"i2c - I2C sub-system\n",
|
|
#if defined(CONFIG_I2C_MULTI_BUS)
|
|
"dev [dev] - show or set current I2C bus\n"
|
|
#endif /* CONFIG_I2C_MULTI_BUS */
|
|
"i2c speed [speed] - show or set I2C bus speed\n"
|
|
"i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
|
|
"i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
|
|
"i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
|
|
"i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
|
|
"i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
|
|
"i2c probe - show devices on the I2C bus\n"
|
|
"i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
|
|
#if defined(CONFIG_CMD_SDRAM)
|
|
"i2c sdram chip - print SDRAM configuration information\n"
|
|
#endif
|
|
);
|
|
#endif /* CONFIG_I2C_CMD_TREE */
|
|
U_BOOT_CMD(
|
|
imd, 4, 1, do_i2c_md, \
|
|
"imd - i2c memory display\n", \
|
|
"chip address[.0, .1, .2] [# of objects]\n - i2c memory display\n" \
|
|
);
|
|
|
|
U_BOOT_CMD(
|
|
imm, 3, 1, do_i2c_mm,
|
|
"imm - i2c memory modify (auto-incrementing)\n",
|
|
"chip address[.0, .1, .2]\n"
|
|
" - memory modify, auto increment address\n"
|
|
);
|
|
U_BOOT_CMD(
|
|
inm, 3, 1, do_i2c_nm,
|
|
"inm - memory modify (constant address)\n",
|
|
"chip address[.0, .1, .2]\n - memory modify, read and keep address\n"
|
|
);
|
|
|
|
U_BOOT_CMD(
|
|
imw, 5, 1, do_i2c_mw,
|
|
"imw - memory write (fill)\n",
|
|
"chip address[.0, .1, .2] value [count]\n - memory write (fill)\n"
|
|
);
|
|
|
|
U_BOOT_CMD(
|
|
icrc32, 5, 1, do_i2c_crc,
|
|
"icrc32 - checksum calculation\n",
|
|
"chip address[.0, .1, .2] count\n - compute CRC32 checksum\n"
|
|
);
|
|
|
|
U_BOOT_CMD(
|
|
iprobe, 1, 1, do_i2c_probe,
|
|
"iprobe - probe to discover valid I2C chip addresses\n",
|
|
"\n -discover valid I2C chip addresses\n"
|
|
);
|
|
|
|
/*
|
|
* Require full name for "iloop" because it is an infinite loop!
|
|
*/
|
|
U_BOOT_CMD(
|
|
iloop, 5, 1, do_i2c_loop,
|
|
"iloop - infinite loop on address range\n",
|
|
"chip address[.0, .1, .2] [# of objects]\n"
|
|
" - loop, reading a set of addresses\n"
|
|
);
|
|
|
|
#if defined(CONFIG_CMD_SDRAM)
|
|
U_BOOT_CMD(
|
|
isdram, 2, 1, do_sdram,
|
|
"isdram - print SDRAM configuration information\n",
|
|
"chip\n - print SDRAM configuration information\n"
|
|
" (valid chip values 50..57)\n"
|
|
);
|
|
#endif
|