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56882dc4cb
On mvebu this is defined if and only if !ARM64. Otherwise it is defined for boards with ARCH_MX23, ARCH_TEGRA and ARCH_ZYNQ, and also for SOC_AR934X (tplink_wdr4300). Signed-off-by: Marek Behún <marek.behun@nic.cz>
61 lines
2.0 KiB
C
61 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010-2012
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _TEGRA30_COMMON_H_
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#define _TEGRA30_COMMON_H_
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#include "tegra-common.h"
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_STACKBASE 0x83800000 /* 56MB */
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/*
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* Memory layout for where various images get loaded by boot scripts:
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*
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* scriptaddr can be pretty much anywhere that doesn't conflict with something
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* else. Put it above BOOTMAPSZ to eliminate conflicts.
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*
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* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
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* something else. Put it above BOOTMAPSZ to eliminate conflicts.
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*
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* kernel_addr_r must be within the first 128M of RAM in order for the
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* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
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* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
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* should not overlap that area, or the kernel will have to copy itself
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* somewhere else before decompression. Similarly, the address of any other
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* data passed to the kernel shouldn't overlap the start of RAM. Pushing
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* this up to 32M allows for a sizable kernel to be decompressed below the
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* compressed load address.
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*
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* fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
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* the compressed kernel to be up to 32M too.
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*
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* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
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* for the FDT/DTB to be up to 1M, which is hopefully plenty.
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*/
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#define MEM_LAYOUT_ENV_SETTINGS \
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"scriptaddr=0x90000000\0" \
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"pxefile_addr_r=0x90100000\0" \
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"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"fdtfile=" FDTFILE "\0" \
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"fdt_addr_r=0x83000000\0" \
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"ramdisk_addr_r=0x83100000\0"
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/* Defines for SPL */
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#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
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#define CONFIG_SPL_STACK 0x800ffffc
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/* For USB EHCI controller */
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#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
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#endif /* _TEGRA30_COMMON_H_ */
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