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a9ee1ad95a
We only set one of these values ever at this point, so remove dead code. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011 Samsung Electronics
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*
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* Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "exynos4-common.h"
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#undef CONFIG_USB_GADGET_DWC2_OTG_PHY
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/* High Level Configuration Options */
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#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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/* Handling Sleep Mode*/
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#define S5P_CHECK_SLEEP 0x00000BAD
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#define S5P_CHECK_DIDLE 0xBAD00000
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#define S5P_CHECK_LPA 0xABAD0000
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/* MMC SPL */
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#define COPY_BL2_FNPTR_ADDR 0x00002488
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/* SMDKV310 has 4 bank of DRAM */
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#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
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#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
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#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
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/* FLASH and environment organization */
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/* MIU (Memory Interleaving Unit) */
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#define CONFIG_MIU_2BIT_INTERLEAVED
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#define RESERVE_BLOCK_SIZE (512)
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#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
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#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
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#define CONFIG_SYS_INIT_SP_ADDR 0x02040000
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/* Ethernet Controllor Driver */
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#ifdef CONFIG_CMD_NET
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#define CONFIG_ENV_SROM_BANK 1
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#endif /*CONFIG_CMD_NET*/
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#endif /* __CONFIG_H */
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