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36a4dae18f
There are a handful of variants around CONFIG_SYS_USE_DATAFLASH and none of them now control anything further within their board config.h files, so remove these from CONFIG_SYS_EXTRA_OPTIONS and then remove the empty blocks in the board config.h files. In a few places further clean up related logic. Signed-off-by: Tom Rini <trini@konsulko.com>
50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* Configuation settings for the AT91SAM9RLEK board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/hardware.h>
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
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/*
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* Hardware drivers
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*/
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/* LCD */
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#define LCD_BPP LCD_COLOR8
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/* Let board_init_f handle the framebuffer allocation */
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#undef CONFIG_FB_ADDR
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/* SDRAM */
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000
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#define CONFIG_SYS_INIT_SP_ADDR \
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(ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_DBW_8 1
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
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#endif
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#endif
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