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0154e6de37
Drop legacy #define CONFIG_DRIVER_DM9000 from board include/configs/ and enable the same in Kconfig configs/ . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
67 lines
1.7 KiB
C
67 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* Configuation settings for the AT91SAM9261EK board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
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#include <asm/hardware.h>
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/*
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* Hardware drivers
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*/
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/* LCD */
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#define LCD_BPP LCD_COLOR8
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/* SDRAM */
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000
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#define CONFIG_SYS_INIT_SP_ADDR \
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(ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8
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/* our ALE is AD22 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
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/* our CLE is AD21 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
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#endif
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/* Ethernet */
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#define CONFIG_DM9000_BASE 0x30000000
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#define DM9000_IO CONFIG_DM9000_BASE
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#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
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#define CONFIG_DM9000_USE_16BIT
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#define CONFIG_DM9000_NO_SROM
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/* USB */
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
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#ifdef CONFIG_AT91SAM9G10EK
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10"
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#else
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
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#endif
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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#endif
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