mirror of
https://github.com/u-boot/u-boot.git
synced 2024-12-16 16:23:33 +08:00
9307cbaba9
U-boot binary size has been increased from 512KB to 768KB. So update CONFIG_SYS_MONITOR_LEN to reflect the same. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
524 lines
16 KiB
C
524 lines
16 KiB
C
/*
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* Copyright 2010-2012 Freescale Semiconductor, Inc.
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*
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* Authors: Roy Zang <tie-fei.zang@freescale.com>
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* Chunhe Lan <b25806@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* p1023rds board configuration file
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef CONFIG_NAND
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#define CONFIG_NAND_U_BOOT
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#define CONFIG_RAMBOOT_NAND
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#endif
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#ifdef CONFIG_NAND_U_BOOT
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#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
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#else
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#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif /* CONFIG_NAND_SPL */
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#endif
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xeff40000
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#endif
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#ifndef CONFIG_SYS_MONITOR_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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/* High Level Configuration Options */
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#define CONFIG_BOOKE /* BOOKE */
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#define CONFIG_E500 /* BOOKE e500 family */
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#define CONFIG_P1023
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#define CONFIG_P1023RDS
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#define CONFIG_MP /* support multiple processors */
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#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
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#define CONFIG_PCI /* Enable PCI/PCIE */
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#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
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#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
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#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#ifndef __ASSEMBLY__
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extern unsigned long get_clock_freq(void);
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#endif
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#define CONFIG_SYS_CLK_FREQ 66666666
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#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_HWCONFIG
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#define CONFIG_ENABLE_36BIT_PHYS
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#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x1fffffff /* fix me, only 1G */
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#define CONFIG_PANIC_HANG /* do not reset board on panic */
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#define CONFIG_SYS_LBC_LBCR 0x00000000 /* Implement conversion of
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addresses in the LBC */
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/* DDR Setup */
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 2
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/* These are used when DDR doesn't use SPD. */
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#define CONFIG_SYS_SDRAM_SIZE 2048u /* DDR is 2GB */
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/* Default settings for "stable" mode */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
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#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
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#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
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#define CONFIG_SYS_DDR_TIMING_3 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0 0x40110104
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#define CONFIG_SYS_DDR_TIMING_1 0x5C59E544
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#define CONFIG_SYS_DDR_TIMING_2 0x0fA888CA
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#define CONFIG_SYS_DDR_MODE_1 0x00441210
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#define CONFIG_SYS_DDR_MODE_2 0x00000000
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#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL 0x0A280100
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#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
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#define CONFIG_SYS_DDR_CLK_CTRL 0x01800000
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#define CONFIG_SYS_DDR_TIMING_4 0x00000001
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#define CONFIG_SYS_DDR_TIMING_5 0x01401400
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#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
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#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F605
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#define CONFIG_SYS_DDR_CONTROL 0xC70C0008 /* Type = DDR3: No Interleaving */
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#define CONFIG_SYS_DDR_CONTROL2 0x24401010
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#define CONFIG_SYS_DDR_CDR1 0x00000000
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#define CONFIG_SYS_DDR_CDR2 0x00000000
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#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
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#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
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#define CONFIG_SYS_DDR_SBE 0x00000000
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/* Settings that differ for "performance" mode */
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#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
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#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
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#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014302
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#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5C58E544
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#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0FA888CA
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/* Type = DDR3: cs0-cs1 interleaving */
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#define CONFIG_SYS_DDR_CONTROL_PERF 0xC70C4008
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#define CONFIG_SYS_DDR_CDR_1 0x00000000
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#define CONFIG_SYS_DDR_CDR_2 0x00000000
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/*
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* Memory map
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
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* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
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* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
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* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
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*
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* Localbus non-cacheable
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* 0xe000_0000 0xe003_ffff BCSR 256K BCSR
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* 0xee00_0000 0xefff_ffff NOR flash 32M NOR flash
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* 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M
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* 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
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* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
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* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
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*/
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */
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#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
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#ifndef CONFIG_NAND
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#define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
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| BR_PS_16 | BR_V)
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#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#else
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#define CONFIG_SYS_NO_FLASH
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#endif
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#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
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#define CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */
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#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
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#ifndef CONFIG_NAND_SPL
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#define CONFIG_SYS_NAND_BASE 0xffa00000
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#else
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#define CONFIG_SYS_NAND_BASE 0xfff00000
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#endif
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#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_CMD_NAND
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#define CONFIG_NAND_FSL_ELBC
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#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
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/* NAND boot: 4K NAND loader config */
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#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
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#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
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#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
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#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
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/* NAND flash config */
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#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#ifdef CONFIG_RAMBOOT_NAND
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/* NAND Base Address */
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#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
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#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
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/* chip select 1 - BCSR */
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#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
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| BR_MS_GPCM | BR_PS_8 | BR_V)
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#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
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| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
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| OR_GPCM_EAD)
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#else
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#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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/* chip select 1 - BCSR */
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#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
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| BR_MS_GPCM | BR_PS_8 | BR_V)
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#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
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| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
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| OR_GPCM_EAD)
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#endif
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/* Serial Port
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* open - index 2
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* shorted - index 1
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*/
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_NS16550_MIN_FUNCTIONS
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#endif
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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/*
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* Pass open firmware flat tree
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*/
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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#define CONFIG_OF_STDOUT_VIA_ALIAS
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/* new uImage format support */
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#define CONFIG_FIT
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#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
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/*
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* I2C2 EEPROM
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*/
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#define CONFIG_ID_EEPROM
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#ifdef CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#endif
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_CMD_I2C
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/*
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* eSPI - Enhanced SPI
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*/
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_ATMEL
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#define CONFIG_HARD_SPI
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#define CONFIG_FSL_ESPI
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#define CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE 0
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 3, Slot 1, tgtid 3, Base address b000 */
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#define CONFIG_SYS_PCIE3_NAME "Slot 3"
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
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#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
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#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
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#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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/* controller 2, direct to uli, tgtid 2, Base address 9000 */
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#define CONFIG_SYS_PCIE2_NAME "Slot 2"
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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/* controller 1, Slot 2, tgtid 1, Base address a000 */
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#define CONFIG_SYS_PCIE1_NAME "Slot 1"
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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#if defined(CONFIG_PCI)
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#define CONFIG_E1000 /* Defind e1000 pci Ethernet card */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif /* CONFIG_PCI */
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/*
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* Environment
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*/
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_SYS_RAMBOOT)
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#if defined(CONFIG_RAMBOOT_NAND)
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
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#else
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#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
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#endif
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#define CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_SETEXPR
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#define CONFIG_CMD_REGINFO
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_NET
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#endif
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/*
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* USB
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*/
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#define CONFIG_HAS_FSL_DR_USB
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#ifdef CONFIG_HAS_FSL_DR_USB
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#define CONFIG_USB_EHCI
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#ifdef CONFIG_USB_EHCI
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#define CONFIG_CMD_USB
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_USB_EHCI_FSL
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|
#define CONFIG_USB_STORAGE
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|
#define CONFIG_CMD_FAT
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|
#define CONFIG_CMD_EXT2
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|
#define CONFIG_CMD_FAT
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|
#define CONFIG_DOS_PARTITION
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|
#endif
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|
#endif
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|
|
|
/*
|
|
* Miscellaneous configurable options
|
|
*/
|
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
|
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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|
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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|
#if defined(CONFIG_CMD_KGDB)
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|
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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|
#else
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|
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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|
#endif
|
|
/* Print Buffer Size */
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|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
|
|
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
|
/* Boot Argument Buffer Size */
|
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
|
|
|
/*
|
|
* For booting Linux, the board info and command line data
|
|
* have to be in the first 16 MB of memory, since this is
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
*/
|
|
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
|
|
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
|
#endif
|
|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
#define CONFIG_BOOTFILE "uImage"
|
|
#define CONFIG_UBOOTPATH (u-boot.bin) /* U-Boot image on TFTP server */
|
|
|
|
/* default location for tftp and bootm */
|
|
#define CONFIG_LOADADDR 1000000
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|
|
|
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
|
|
|
|
#define CONFIG_BAUDRATE 115200
|
|
|
|
/* Qman/Bman */
|
|
#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */
|
|
#define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
|
|
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
|
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
|
|
#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
|
|
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
|
#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
|
|
|
|
/* For FM */
|
|
#define CONFIG_SYS_DPAA_FMAN
|
|
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
|
|
|
#ifdef CONFIG_SYS_DPAA_FMAN
|
|
#define CONFIG_FMAN_ENET
|
|
#define CONFIG_PHY_MARVELL
|
|
#endif
|
|
|
|
#ifndef CONFIG_NAND
|
|
/* Default address of microcode for the Linux Fman driver */
|
|
/* QE microcode/firmware address */
|
|
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
|
|
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
|
|
#else
|
|
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
|
|
#define CONFIG_SYS_FMAN_FW_ADDR 0x1f00000
|
|
#endif
|
|
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
|
|
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
|
|
|
|
#ifdef CONFIG_FMAN_ENET
|
|
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
|
|
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x7
|
|
|
|
#define CONFIG_SYS_TBIPA_VALUE 8
|
|
#define CONFIG_MII /* MII PHY management */
|
|
#define CONFIG_ETHPRIME "FM1@DTSEC1"
|
|
#endif
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
|
|
|
|
#endif /* __CONFIG_H */
|