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786a08e0dd
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
65 lines
1.7 KiB
C
65 lines
1.7 KiB
C
/*
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*
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* Copyright (c) 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _X86_CHROMEBOOK_H
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#define _X86_CHROMEBOOK_H
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#define CONFIG_SYS_MONITOR_LEN (1 << 20)
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#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_MISC_INIT_R
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#define CONFIG_X86_MRC_ADDR 0xfffa0000
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#define CONFIG_CACHE_MRC_SIZE_KB 512
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#define CONFIG_X86_SERIAL
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#define CONFIG_SCSI_DEV_LIST \
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}
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#define CONFIG_PCI_MEM_BUS 0xe0000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_PREF_BUS 0xd0000000
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#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
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#define CONFIG_PCI_PREF_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x1000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0xefff
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#define CONFIG_SYS_EARLY_PCI_INIT
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#define CONFIG_PCI_PNP
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#define CONFIG_BIOSEMU
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#define VIDEO_IO_OFFSET 0
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#define CONFIG_X86EMU_RAW_IO
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#define CONFIG_CROS_EC
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#define CONFIG_CROS_EC_LPC
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#define CONFIG_CMD_CROS_EC
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#define CONFIG_ARCH_EARLY_INIT_R
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#undef CONFIG_ENV_IS_NOWHERE
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#undef CONFIG_ENV_SIZE
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#define CONFIG_ENV_SIZE 0x1000
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#define CONFIG_ENV_SECT_SIZE 0x1000
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET 0x003f8000
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#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
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"stdout=vga,serial\0" \
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"stderr=vga,serial\0"
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#endif
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