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c7430d7d5e
MX6Q/QP IPU operates at 264MHz and MX6DL IPU at 198MHz. When running a SPL target, which supports multiple MX6 variants we cannot properly setup the IPU clock frequency via CONFIG_IPUV3_CLK option as such decision is done in build-time currently. Remove the CONFIG_IPUV3_CLK option and let the IPU clock frequency be configured in run-time on mx6. Reported-by: Eric Nelson <eric@nelint.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stefano Babic <sbabic@denx.de> [agust: fixed #endif in cgtqmx6eval.h] Signed-off-by: Anatolij Gustschin <agust@denx.de>
167 lines
4.4 KiB
C
167 lines
4.4 KiB
C
/*
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* Copyright (C) 2014 Soeren Moch <smoch@web.de>
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*
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* Configuration settings for the TBS2910 MatrixARM board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __TBS2910_CONFIG_H
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#define __TBS2910_CONFIG_H
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#include "mx6_common.h"
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/* General configuration */
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#define CONFIG_MACH_TYPE 3980
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_IMX_THERMAL
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END \
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(CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
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#define CONFIG_SYS_BOOTMAPSZ 0x10000000
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/* Serial console */
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
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#define CONFIG_CONS_INDEX 1
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/* Filesystems / image support */
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/* MMC */
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#define CONFIG_SYS_FSL_USDHC_NUM 3
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#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
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#define CONFIG_SUPPORT_EMMC_BOOT
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/* Ethernet */
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_MXC
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#define CONFIG_MII
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 4
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#define CONFIG_PHY_ATHEROS
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/* Framebuffer */
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#ifdef CONFIG_VIDEO
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#define CONFIG_VIDEO_IPUV3
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_IMX_HDMI
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#define CONFIG_IMX_VIDEO_SKIP
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#endif
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/* PCI */
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#ifdef CONFIG_CMD_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_PCIE_IMX
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#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
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#endif
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/* SATA */
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#ifdef CONFIG_CMD_SATA
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#define CONFIG_DWC_AHSATA
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#define CONFIG_SYS_SATA_MAX_DEVICE 1
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#define CONFIG_DWC_AHSATA_PORT_ID 0
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#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
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#define CONFIG_LBA48
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#define CONFIG_LIBATA
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#endif
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/* USB */
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#ifdef CONFIG_CMD_USB_MASS_STORAGE
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#define CONFIG_USBD_HS
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#define CONFIG_USB_FUNCTION_MASS_STORAGE
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#endif /* CONFIG_CMD_USB_MASS_STORAGE */
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#ifdef CONFIG_USB_KEYBOARD
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#define CONFIG_PREBOOT \
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"usb start; " \
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"if hdmidet; then " \
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"run set_con_hdmi; " \
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"else " \
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"run set_con_serial; " \
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"fi;"
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#endif /* CONFIG_USB_KEYBOARD */
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#endif /* CONFIG_CMD_USB */
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/* RTC */
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#ifdef CONFIG_CMD_DATE
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#define CONFIG_RTC_DS1307
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#define CONFIG_SYS_RTC_BUS_NUM 2
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#endif
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/* I2C */
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#ifdef CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_I2C_EDID
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#endif
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/* Environment organization */
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#define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */
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#define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */
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#define CONFIG_ENV_SIZE (8 * 1024)
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#define CONFIG_ENV_OFFSET (384 * 1024)
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
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"bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
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"video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
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"bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
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"bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
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"${bootargs_mmc3}\0" \
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"bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
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"rdinit=/sbin/init enable_wait_mode=off\0" \
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"bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
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"mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \
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"bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
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"bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
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"run bootargs_upd; " \
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"bootm 0x10800000 0x10d00000\0" \
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"console=ttymxc0\0" \
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"fan=gpio set 92\0" \
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"set_con_serial=setenv stdout serial; " \
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"setenv stderr serial;\0" \
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"set_con_hdmi=setenv stdout serial,vga; " \
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"setenv stderr serial,vga;\0" \
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"stderr=serial,vga;\0" \
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"stdin=serial,usbkbd;\0" \
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"stdout=serial,vga;\0"
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#define CONFIG_BOOTCOMMAND \
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"mmc rescan; " \
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"if run bootcmd_up1; then " \
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"run bootcmd_up2; " \
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"else " \
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"run bootcmd_mmc; " \
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"fi"
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#endif /* __TBS2910_CONFIG_H * */
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