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c7430d7d5e
MX6Q/QP IPU operates at 264MHz and MX6DL IPU at 198MHz. When running a SPL target, which supports multiple MX6 variants we cannot properly setup the IPU clock frequency via CONFIG_IPUV3_CLK option as such decision is done in build-time currently. Remove the CONFIG_IPUV3_CLK option and let the IPU clock frequency be configured in run-time on mx6. Reported-by: Eric Nelson <eric@nelint.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Reviewed-by: Stefano Babic <sbabic@denx.de> [agust: fixed #endif in cgtqmx6eval.h] Signed-off-by: Anatolij Gustschin <agust@denx.de>
243 lines
6.7 KiB
C
243 lines
6.7 KiB
C
/*
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*
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* Congatec Conga-QEVAl board configuration file.
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*
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* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
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* Based on Freescale i.MX6Q Sabre Lite board configuration file.
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* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
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* Leo Sartre, <lsartre@adeneo-embedded.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_CGTQMX6EVAL_H
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#define __CONFIG_CGTQMX6EVAL_H
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#include "mx6_common.h"
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#define CONFIG_MACH_TYPE 4122
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#ifdef CONFIG_SPL
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#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
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#define CONFIG_SPL_SPI_LOAD
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#include "imx6_spl.h"
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#endif
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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#define CONFIG_MISC_INIT_R
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART2_BASE
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/* MMC Configs */
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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/* SPI NOR */
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_SPI_FLASH_SST
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#define CONFIG_MXC_SPI
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#define CONFIG_SF_DEFAULT_BUS 0
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
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/* Thermal support */
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#define CONFIG_IMX_THERMAL
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_SPEED 100000
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/* PMIC */
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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#define CONFIG_POWER_PFUZE100
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#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
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/* USB Configs */
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
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#define CONFIG_USBD_HS
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#define CONFIG_USB_FUNCTION_MASS_STORAGE
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/* Framebuffer */
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#define CONFIG_VIDEO_IPUV3
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_SPLASH_SCREEN_ALIGN
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_IMX_HDMI
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/* SATA */
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#define CONFIG_DWC_AHSATA
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#define CONFIG_SYS_SATA_MAX_DEVICE 1
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#define CONFIG_DWC_AHSATA_PORT_ID 0
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#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
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#define CONFIG_LBA48
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#define CONFIG_LIBATA
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/* Ethernet */
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#define CONFIG_FEC_MXC
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#define CONFIG_MII
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 6
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#define CONFIG_PHY_ATHEROS
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/* Command definition */
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#define CONFIG_MXC_UART_BASE UART2_BASE
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#define CONSOLE_DEV "ttymxc1"
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#define CONFIG_MMCROOT "/dev/mmcblk0p2"
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"image=zImage\0" \
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"fdtfile=undefined\0" \
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"fdt_addr_r=0x18000000\0" \
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"boot_fdt=try\0" \
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"ip_dyn=yes\0" \
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"console=" CONSOLE_DEV "\0" \
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"dfuspi=dfu 0 sf 0:0:10000000:0\0" \
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"dfu_alt_info_spl=spl raw 0x400\0" \
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"dfu_alt_info_img=u-boot raw 0x10000\0" \
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"dfu_alt_info=spl raw 0x400\0" \
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"bootm_size=0x10000000\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"update_sd_firmware=" \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"if mmc dev ${mmcdev}; then " \
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"if ${get_cmd} ${update_sd_firmware_filename}; then " \
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"setexpr fw_sz ${filesize} / 0x200; " \
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"setexpr fw_sz ${fw_sz} + 1; " \
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"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
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"fi; " \
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"fi\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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"loadbootscript=" \
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"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if run loadfdt; then " \
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"bootz ${loadaddr} - ${fdt_addr_r}; " \
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"else " \
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"if test ${boot_fdt} = try; then " \
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"bootz; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi; " \
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"else " \
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"bootz; " \
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"fi;\0" \
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"findfdt="\
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"if test $board_rev = MX6Q ; then " \
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"setenv fdtfile imx6q-qmx6.dtb; fi; " \
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"if test $board_rev = MX6DL ; then " \
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"setenv fdtfile imx6dl-qmx6.dtb; fi; " \
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"if test $fdtfile = undefined; then " \
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"echo WARNING: Could not determine dtb to use; fi; \0" \
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"netargs=setenv bootargs console=${console},${baudrate} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${image}; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
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"bootz ${loadaddr} - ${fdt_addr_r}; " \
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"else " \
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"if test ${boot_fdt} = try; then " \
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"bootz; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi; " \
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"else " \
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"bootz; " \
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"fi;\0" \
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"spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\
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#define CONFIG_BOOTCOMMAND \
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"run spilock;" \
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"run findfdt; " \
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"mmc dev ${mmcdev};" \
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"if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loadimage; then " \
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"run mmcboot; " \
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"else run netboot; " \
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"fi; " \
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"fi; " \
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"else run netboot; fi"
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#define CONFIG_SYS_MEMTEST_START 0x10000000
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#define CONFIG_SYS_MEMTEST_END 0x10010000
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#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* Environment organization */
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#if defined (CONFIG_ENV_IS_IN_MMC)
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#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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#define CONFIG_ENV_SIZE (8 * 1024)
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#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
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#define CONFIG_ENV_OFFSET (768 * 1024)
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
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#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
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#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
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#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
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#endif
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#endif /* __CONFIG_CGTQMX6EVAL_H */
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