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c2ae7d8220
Move the SPL settings into common/spl where most of the SPL code is kept. Signed-off-by: Simon Glass <sjg@chromium.org>
25 lines
761 B
Plaintext
25 lines
761 B
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_SUNXI=y
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CONFIG_MACH_SUN8I_A23=y
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CONFIG_DRAM_CLK=552
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CONFIG_DRAM_ZQ=63351
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CONFIG_MMC0_CD_PIN="PB4"
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CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
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CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
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CONFIG_USB0_ID_DET="PH8"
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CONFIG_AXP_GPIO=y
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CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0"
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CONFIG_VIDEO_LCD_DCLK_PHASE=0
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CONFIG_VIDEO_LCD_POWER="PH7"
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CONFIG_VIDEO_LCD_BL_EN="PH6"
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CONFIG_VIDEO_LCD_BL_PWM="PH0"
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CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-inet86dz"
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
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CONFIG_SPL=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FPGA is not set
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CONFIG_AXP_DLDO1_VOLT=3300
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CONFIG_USB_MUSB_HOST=y
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