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910feb50d4
With the exception of how PowerPC handles SPL and TPL (which has its own issues), we cannot safely hide options under CONFIG_SPL_BUILD. Largely remove the places that have this test today. Signed-off-by: Tom Rini <trini@konsulko.com>
66 lines
1.4 KiB
C
66 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Allied Telesis Labs
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*/
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#ifndef _CONFIG_X530_H
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#define _CONFIG_X530_H
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/*
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* High Level Configuration Options (easy to change)
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*/
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
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#if !defined(CONFIG_DM_SERIAL)
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
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#endif
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/*
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* Serial Port configuration
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* The following definitions let you select what serial you want to use
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* for your console driver.
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*/
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/* NAND */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define BBT_CUSTOM_SCAN
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#define BBT_CUSTOM_SCAN_PAGE 0
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#define BBT_CUSTOM_SCAN_POSITION 2048
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/* SPI NOR flash default params, used by sf commands */
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#define MTDIDS_DEFAULT "nand0=nand"
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#define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)"
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#define MTDPARTS_MTDOOPS "errlog"
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/* Partition support */
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/* Additional FS support/configuration */
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/* Environment in SPI NOR flash */
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
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/* PCIe support */
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#define CONFIG_PCI_SCAN_SHOW
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/* NAND */
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#include <asm/arch/config.h>
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/* Keep device tree and initrd in low memory so the kernel can access them */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0x10000000\0" \
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"initrd_high=0x10000000\0"
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#define CONFIG_UBI_PART user
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#define CONFIG_UBIFS_VOLUME user
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#endif /* _CONFIG_X530_H */
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