mirror of
https://github.com/u-boot/u-boot.git
synced 2024-12-04 01:53:27 +08:00
eaf6ea6a1d
- Make all users of CUSTOM_SYS_INIT_SP_ADDR reference SYS_INIT_SP_ADDR - Introduce HAS_CUSTOM_SYS_INIT_SP_ADDR to allow for setting the stack pointer directly, otherwise we use the common calculation. - On some platforms that were using the standard calculation but did not set CONFIG_SYS_INIT_RAM_SIZE / CONFIG_SYS_INIT_RAM_ADDR, set them. - On a small number of platforms that were not subtracting GENERATED_GBL_DATA_SIZE do so now via the standard calculation. - CONFIG_SYS_INIT_SP_OFFSET is now widely unused, so remove it from most board config header files. Signed-off-by: Tom Rini <trini@konsulko.com>
111 lines
3.8 KiB
C
111 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020 Synopsys, Inc. All rights reserved.
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* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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*/
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#ifndef _CONFIG_HSDK_H_
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#define _CONFIG_HSDK_H_
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#include <linux/sizes.h>
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/*
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* CPU configuration
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*/
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#define NR_CPUS 4
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#define ARC_PERIPHERAL_BASE 0xF0000000
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#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
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#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
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/*
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* Memory configuration
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*/
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_SDRAM_SIZE SZ_1G
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#define CONFIG_SYS_BOOTM_LEN SZ_128M
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/*
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* UART configuration
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_CLK 33330000
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#define CONFIG_SYS_NS16550_MEM32
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/*
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* Ethernet PHY configuration
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*/
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/*
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* USB 1.1 configuration
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*/
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
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/*
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* Environment settings
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"upgrade=if mmc rescan && " \
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"fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
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"iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
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"\"Fail to upgrade.\n" \
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"Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \
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"; fi\0" \
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"core_mask=0xF\0" \
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"hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
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setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \
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setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
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setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
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"hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
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setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
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setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
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setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
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"hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
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setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
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setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
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setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
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"hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
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setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
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setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
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setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
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"hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
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setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
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setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
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setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
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"hsdk_hs48x2=run hsdk_hs47dx2;\0" \
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"hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \
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setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
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setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
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setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
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setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
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"hsdk_hs48x3=run hsdk_hs47dx3;\0" \
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"hsdk_hs47dx3=setenv core_mask 0x7; setenv haps_apb_location 0x1; \
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setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
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setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
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setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
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setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
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setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
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"hsdk_hs48x4=run hsdk_hs47dx4;\0" \
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"hsdk_hs47dx4=setenv core_mask 0xF; setenv haps_apb_location 0x1; \
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setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
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setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
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setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF; \
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setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
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setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
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setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
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/*
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* Environment configuration
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*/
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/* Cli configuration */
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/*
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* Callback configuration
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*/
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#endif /* _CONFIG_HSDK_H_ */
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