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https://github.com/u-boot/u-boot.git
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9cebc4ad8e
We move the existing CONFIG_POST_* functionality over to CFG_POST and then introduce CONFIG_POST to Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
111 lines
2.7 KiB
Plaintext
111 lines
2.7 KiB
Plaintext
CONFIG_PPC=y
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CONFIG_TEXT_BASE=0xFFF40000
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CONFIG_SYS_MALLOC_LEN=0x100000
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_OFFSET=0xCF400
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CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
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CONFIG_MPC85xx=y
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CONFIG_SYS_INIT_RAM_LOCK=y
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CONFIG_SYS_SRIO=y
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CONFIG_SRIO1=y
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CONFIG_SRIO2=y
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CONFIG_SRIO_PCIE_BOOT_MASTER=y
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CONFIG_TARGET_P2041RDB=y
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CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
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CONFIG_ENABLE_36BIT_PHYS=y
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CONFIG_SYS_BOOK3E_HV=y
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CONFIG_SYS_CACHE_STASHING=y
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CONFIG_PCIE1=y
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CONFIG_PCIE2=y
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CONFIG_PCIE3=y
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CONFIG_SYS_FSL_NUM_CC_PLLS=2
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CONFIG_SYS_MONITOR_LEN=786432
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_DYNAMIC_SYS_CLK_FREQ=y
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CONFIG_RAMBOOT_PBL=y
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CONFIG_SYS_FSL_PBL_PBI="board/freescale/p2041rdb/pbi.cfg"
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CONFIG_SYS_FSL_PBL_RCW="board/freescale/p2041rdb/rcw_p2041rdb.cfg"
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CONFIG_BOOTDELAY=10
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CONFIG_USE_BOOTCOMMAND=y
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CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/$bdev rw console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
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CONFIG_ARCH_MISC_INIT=y
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_ID_EEPROM=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PBSIZE=276
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_GREPENV=y
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
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CONFIG_CMD_DM=y
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CONFIG_CMD_I2C=y
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CONFIG_LOADS_ECHO=y
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CONFIG_SYS_LOADS_BAUD_CHANGE=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_FAT=y
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_USE_BOOTFILE=y
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CONFIG_BOOTFILE="uImage"
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CONFIG_USE_ETHPRIME=y
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CONFIG_ETHPRIME="FM1@DTSEC1"
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CONFIG_FSL_SATA_V2=y
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CONFIG_SYS_SATA_MAX_DEVICE=2
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CONFIG_FSL_CAAM=y
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CONFIG_SYS_BR0_PRELIM_BOOL=y
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CONFIG_SYS_BR0_PRELIM=0xE8001001
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CONFIG_SYS_OR0_PRELIM=0xF8000F85
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CONFIG_SYS_BR3_PRELIM_BOOL=y
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CONFIG_SYS_BR3_PRELIM=0xFFDF0801
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CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
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CONFIG_DM_I2C=y
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CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
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CONFIG_SYS_I2C_FSL=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x50
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_EMPTY_INFO=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_SYS_FLASH_QUIET_TEST=y
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CONFIG_SYS_MAX_FLASH_SECT=1024
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_SPEED=10000000
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB_10G=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_DM_MDIO=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_FMAN_ENET=y
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CONFIG_SYS_FMAN_FW_ADDR=0xD2000
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CONFIG_MII=y
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CONFIG_PCIE_FSL=y
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CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
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CONFIG_SYS_NS16550_SERIAL=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_FSL_ESPI=y
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CONFIG_USB=y
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CONFIG_USB_EHCI_FSL=y
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CONFIG_USB_MAX_CONTROLLER_COUNT=2
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CONFIG_USB_STORAGE=y
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CONFIG_ADDR_MAP=y
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CONFIG_SYS_NUM_ADDR_MAP=64
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CONFIG_POST=y
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