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https://github.com/u-boot/u-boot.git
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e564f054af
Add a convenience function to access the private data that a uclass stores for each of its devices. Convert over most existing uses for consistency and to provide an example for others. Signed-off-by: Simon Glass <sjg@chromium.org>
382 lines
8.7 KiB
C
382 lines
8.7 KiB
C
/*
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* (C) Copyright 2009 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <dm/device-internal.h>
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#include <dt-bindings/gpio/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define S5P_GPIO_GET_PIN(x) (x % GPIO_PER_BANK)
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#define CON_MASK(val) (0xf << ((val) << 2))
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#define CON_SFR(gpio, cfg) ((cfg) << ((gpio) << 2))
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#define CON_SFR_UNSHIFT(val, gpio) ((val) >> ((gpio) << 2))
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#define DAT_MASK(gpio) (0x1 << (gpio))
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#define DAT_SET(gpio) (0x1 << (gpio))
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#define PULL_MASK(gpio) (0x3 << ((gpio) << 1))
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#define PULL_MODE(gpio, pull) ((pull) << ((gpio) << 1))
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#define DRV_MASK(gpio) (0x3 << ((gpio) << 1))
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#define DRV_SET(gpio, mode) ((mode) << ((gpio) << 1))
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#define RATE_MASK(gpio) (0x1 << (gpio + 16))
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#define RATE_SET(gpio) (0x1 << (gpio + 16))
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/* Platform data for each bank */
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struct exynos_gpio_platdata {
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struct s5p_gpio_bank *bank;
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const char *bank_name; /* Name of port, e.g. 'gpa0" */
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};
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/* Information about each bank at run-time */
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struct exynos_bank_info {
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struct s5p_gpio_bank *bank;
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};
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static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
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{
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const struct gpio_info *data;
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unsigned int upto;
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int i, count;
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data = get_gpio_data();
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count = get_bank_num();
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upto = 0;
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for (i = 0; i < count; i++) {
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debug("i=%d, upto=%d\n", i, upto);
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if (gpio < data->max_gpio) {
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struct s5p_gpio_bank *bank;
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bank = (struct s5p_gpio_bank *)data->reg_addr;
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bank += (gpio - upto) / GPIO_PER_BANK;
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debug("gpio=%d, bank=%p\n", gpio, bank);
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return bank;
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}
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upto = data->max_gpio;
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data++;
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}
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return NULL;
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}
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static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
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{
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unsigned int value;
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value = readl(&bank->con);
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value &= ~CON_MASK(gpio);
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value |= CON_SFR(gpio, cfg);
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writel(value, &bank->con);
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}
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static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
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{
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unsigned int value;
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value = readl(&bank->dat);
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value &= ~DAT_MASK(gpio);
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if (en)
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value |= DAT_SET(gpio);
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writel(value, &bank->dat);
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}
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#ifdef CONFIG_SPL_BUILD
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/* Common GPIO API - SPL does not support driver model yet */
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int gpio_set_value(unsigned gpio, int value)
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{
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s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
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s5p_gpio_get_pin(gpio), value);
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return 0;
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}
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#else
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static int s5p_gpio_get_cfg_pin(struct s5p_gpio_bank *bank, int gpio)
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{
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unsigned int value;
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value = readl(&bank->con);
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value &= CON_MASK(gpio);
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return CON_SFR_UNSHIFT(value, gpio);
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}
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static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
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{
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unsigned int value;
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value = readl(&bank->dat);
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return !!(value & DAT_MASK(gpio));
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}
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#endif /* CONFIG_SPL_BUILD */
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static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
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{
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unsigned int value;
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value = readl(&bank->pull);
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value &= ~PULL_MASK(gpio);
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switch (mode) {
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case S5P_GPIO_PULL_DOWN:
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case S5P_GPIO_PULL_UP:
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value |= PULL_MODE(gpio, mode);
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break;
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default:
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break;
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}
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writel(value, &bank->pull);
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}
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static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
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{
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unsigned int value;
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value = readl(&bank->drv);
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value &= ~DRV_MASK(gpio);
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switch (mode) {
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case S5P_GPIO_DRV_1X:
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case S5P_GPIO_DRV_2X:
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case S5P_GPIO_DRV_3X:
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case S5P_GPIO_DRV_4X:
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value |= DRV_SET(gpio, mode);
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break;
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default:
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return;
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}
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writel(value, &bank->drv);
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}
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static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
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{
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unsigned int value;
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value = readl(&bank->drv);
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value &= ~RATE_MASK(gpio);
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switch (mode) {
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case S5P_GPIO_DRV_FAST:
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case S5P_GPIO_DRV_SLOW:
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value |= RATE_SET(gpio);
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break;
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default:
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return;
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}
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writel(value, &bank->drv);
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}
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int s5p_gpio_get_pin(unsigned gpio)
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{
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return S5P_GPIO_GET_PIN(gpio);
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}
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/* Driver model interface */
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#ifndef CONFIG_SPL_BUILD
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/* set GPIO pin 'gpio' as an input */
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static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct exynos_bank_info *state = dev_get_priv(dev);
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/* Configure GPIO direction as input. */
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s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_INPUT);
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return 0;
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}
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/* set GPIO pin 'gpio' as an output, with polarity 'value' */
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static int exynos_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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struct exynos_bank_info *state = dev_get_priv(dev);
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/* Configure GPIO output value. */
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s5p_gpio_set_value(state->bank, offset, value);
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/* Configure GPIO direction as output. */
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s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_OUTPUT);
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return 0;
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}
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/* read GPIO IN value of pin 'gpio' */
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static int exynos_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct exynos_bank_info *state = dev_get_priv(dev);
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return s5p_gpio_get_value(state->bank, offset);
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}
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/* write GPIO OUT value to pin 'gpio' */
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static int exynos_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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struct exynos_bank_info *state = dev_get_priv(dev);
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s5p_gpio_set_value(state->bank, offset, value);
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return 0;
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}
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#endif /* nCONFIG_SPL_BUILD */
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/*
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* There is no common GPIO API for pull, drv, pin, rate (yet). These
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* functions are kept here to preserve function ordering for review.
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*/
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void gpio_set_pull(int gpio, int mode)
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{
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s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
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s5p_gpio_get_pin(gpio), mode);
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}
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void gpio_set_drv(int gpio, int mode)
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{
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s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
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s5p_gpio_get_pin(gpio), mode);
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}
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void gpio_cfg_pin(int gpio, int cfg)
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{
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s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
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s5p_gpio_get_pin(gpio), cfg);
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}
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void gpio_set_rate(int gpio, int mode)
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{
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s5p_gpio_set_rate(s5p_gpio_get_bank(gpio),
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s5p_gpio_get_pin(gpio), mode);
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}
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#ifndef CONFIG_SPL_BUILD
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static int exynos_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct exynos_bank_info *state = dev_get_priv(dev);
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int cfg;
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cfg = s5p_gpio_get_cfg_pin(state->bank, offset);
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if (cfg == S5P_GPIO_OUTPUT)
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return GPIOF_OUTPUT;
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else if (cfg == S5P_GPIO_INPUT)
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return GPIOF_INPUT;
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else
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return GPIOF_FUNC;
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}
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static int exynos_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
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struct fdtdec_phandle_args *args)
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{
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desc->offset = args->args[0];
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desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
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return 0;
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}
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static const struct dm_gpio_ops gpio_exynos_ops = {
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.direction_input = exynos_gpio_direction_input,
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.direction_output = exynos_gpio_direction_output,
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.get_value = exynos_gpio_get_value,
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.set_value = exynos_gpio_set_value,
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.get_function = exynos_gpio_get_function,
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.xlate = exynos_gpio_xlate,
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};
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static int gpio_exynos_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct exynos_bank_info *priv = dev->priv;
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struct exynos_gpio_platdata *plat = dev->platdata;
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/* Only child devices have ports */
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if (!plat)
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return 0;
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priv->bank = plat->bank;
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uc_priv->gpio_count = GPIO_PER_BANK;
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uc_priv->bank_name = plat->bank_name;
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return 0;
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}
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/**
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* We have a top-level GPIO device with no actual GPIOs. It has a child
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* device for each Exynos GPIO bank.
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*/
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static int gpio_exynos_bind(struct udevice *parent)
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{
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struct exynos_gpio_platdata *plat = parent->platdata;
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struct s5p_gpio_bank *bank, *base;
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const void *blob = gd->fdt_blob;
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int node;
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/* If this is a child device, there is nothing to do here */
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if (plat)
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return 0;
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base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob,
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parent->of_offset, "reg");
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for (node = fdt_first_subnode(blob, parent->of_offset), bank = base;
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node > 0;
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node = fdt_next_subnode(blob, node), bank++) {
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struct exynos_gpio_platdata *plat;
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struct udevice *dev;
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fdt_addr_t reg;
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int ret;
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if (!fdtdec_get_bool(blob, node, "gpio-controller"))
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continue;
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plat = calloc(1, sizeof(*plat));
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if (!plat)
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return -ENOMEM;
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reg = fdtdec_get_addr(blob, node, "reg");
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if (reg != FDT_ADDR_T_NONE)
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bank = (struct s5p_gpio_bank *)((ulong)base + reg);
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plat->bank = bank;
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plat->bank_name = fdt_get_name(blob, node, NULL);
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debug("dev at %p: %s\n", bank, plat->bank_name);
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ret = device_bind(parent, parent->driver,
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plat->bank_name, plat, -1, &dev);
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if (ret)
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return ret;
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dev->of_offset = node;
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}
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return 0;
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}
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static const struct udevice_id exynos_gpio_ids[] = {
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{ .compatible = "samsung,s5pc100-pinctrl" },
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{ .compatible = "samsung,s5pc110-pinctrl" },
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{ .compatible = "samsung,exynos4210-pinctrl" },
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{ .compatible = "samsung,exynos4x12-pinctrl" },
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{ .compatible = "samsung,exynos5250-pinctrl" },
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{ .compatible = "samsung,exynos5420-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(gpio_exynos) = {
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.name = "gpio_exynos",
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.id = UCLASS_GPIO,
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.of_match = exynos_gpio_ids,
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.bind = gpio_exynos_bind,
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.probe = gpio_exynos_probe,
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.priv_auto_alloc_size = sizeof(struct exynos_bank_info),
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.ops = &gpio_exynos_ops,
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};
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#endif
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