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384b1d507f
This patch fixes the warning about misaligned cache on Armada XP: CACHE: Misaligned operation at range [7ffff000, 7fffffac] Signed-off-by: Stefan Roese <sr@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: Tom Rini <trini@konsulko.com>
65 lines
1.5 KiB
C
65 lines
1.5 KiB
C
/*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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const ulong patterns[] = { 0x00000000,
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0xFFFFFFFF,
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0xFF00FF00,
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0x0F0F0F0F,
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0xF0F0F0F0};
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const ulong NBR_OF_PATTERNS = sizeof(patterns) / sizeof(*patterns);
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const ulong OFFS_PATTERN = 3;
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const ulong REPEAT_PATTERN = 1000;
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void bootcount_store(ulong a)
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{
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ulong *save_addr;
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ulong size = 0;
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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size += gd->bd->bi_dram[i].size;
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save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
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writel(a, save_addr);
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writel(BOOTCOUNT_MAGIC, &save_addr[1]);
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for (i = 0; i < REPEAT_PATTERN; i++)
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writel(patterns[i % NBR_OF_PATTERNS],
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&save_addr[i + OFFS_PATTERN]);
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/* Make sure the data is written to RAM */
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flush_dcache_range((ulong)&save_addr[0],
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(((ulong)&save_addr[REPEAT_PATTERN + OFFS_PATTERN] &
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~(ARCH_DMA_MINALIGN - 1)) + ARCH_DMA_MINALIGN));
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}
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ulong bootcount_load(void)
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{
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ulong *save_addr;
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ulong size = 0;
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ulong counter = 0;
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int i, tmp;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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size += gd->bd->bi_dram[i].size;
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save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
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counter = readl(&save_addr[0]);
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/* Is the counter reliable, check in the big pattern for bit errors */
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for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) {
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tmp = readl(&save_addr[i + OFFS_PATTERN]);
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if (tmp != patterns[i % NBR_OF_PATTERNS])
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counter = 0;
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}
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return counter;
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}
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