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219f4788d3
Exactly one board has defined CONFIG_SYS_PROMPT_HUSH_PS2 to a value different than "> " which is vision2. I have Cc'd the maintainer here as I strongly suspect this is a bug rather than intentional behavior. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Stefano Babic <sbabic@denx.de>
196 lines
5.4 KiB
C
196 lines
5.4 KiB
C
/*
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* Copyright (C) 2011
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* Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de>
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*
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* Configuration settings for the grasshopper (ICnova AP7000) board
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __GRASSHOPPER_CONFIG_H
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#define __GRASSHOPPER_CONFIG_H
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#include <asm/arch/hardware.h>
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#define CONFIG_AVR32
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#define CONFIG_AT32AP
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#define CONFIG_AT32AP7000
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/*
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* Timer clock frequency. We're using the CPU-internal COUNT register
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* for this, so this is equivalent to the CPU core clock frequency
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*/
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#define CONFIG_SYS_HZ 1000
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/*
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* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
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* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
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* PLL frequency.
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* (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
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*/
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#define CONFIG_PLL
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#define CONFIG_SYS_POWER_MANAGER
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#define CONFIG_SYS_OSC0_HZ 20000000
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#define CONFIG_SYS_PLL0_DIV 1
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#define CONFIG_SYS_PLL0_MUL 7
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#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
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/*
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* Set the CPU running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
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*/
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#define CONFIG_SYS_CLKDIV_CPU 0
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/*
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* Set the HSB running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
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*/
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#define CONFIG_SYS_CLKDIV_HSB 1
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/*
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* Set the PBA running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
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*/
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#define CONFIG_SYS_CLKDIV_PBA 2
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/*
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* Set the PBB running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
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*/
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#define CONFIG_SYS_CLKDIV_PBB 1
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/* Reserve VM regions for SDRAM and NOR flash */
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#define CONFIG_SYS_NR_VM_REGIONS 2
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/*
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* The PLLOPT register controls the PLL like this:
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* icp = PLLOPT<2>
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* ivco = PLLOPT<1:0>
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*
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* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
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*/
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#define CONFIG_SYS_PLL0_OPT 0x04
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#define CONFIG_USART_BASE ATMEL_BASE_USART1
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#define CONFIG_USART_ID 1
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/* User serviceable stuff */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_STACKSIZE (2048)
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#define CONFIG_BAUDRATE 115200
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/*
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* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
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* data on the serial line may interrupt the boot sequence.
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*/
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#define CONFIG_BOOTDELAY 1
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#define CONFIG_AUTOBOOT
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d" \
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" seconds\n", bootdelay
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#define CONFIG_AUTOBOOT_DELAY_STR "d"
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#define CONFIG_AUTOBOOT_STOP_STR " "
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/*
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* After booting the board for the first time, new ethernet addresses
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* should be generated and assigned to the environment variables
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* "ethaddr". This is normally done during production.
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*/
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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/* remove unneeded commands */
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_SETGETDCR
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/* add useful commands */
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_ATMEL_USART
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#define CONFIG_MACB
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#define CONFIG_PORTMUX_PIO
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#define CONFIG_SYS_NR_PIOS 5
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#define CONFIG_SYS_HSDRAMC
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#define CONFIG_SYS_DCACHE_LINESZ 32
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#define CONFIG_SYS_ICACHE_LINESZ 32
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0x00000000
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#define CONFIG_SYS_FLASH_SIZE 0x800000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 135
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
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#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
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#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
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#define CONFIG_ENV_IS_IN_FLASH
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/* place u-boot env in flash sector after u-boot */
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_ADDR 0x20000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + \
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CONFIG_SYS_INTRAM_SIZE)
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#define CONFIG_SYS_MALLOC_LEN (256*1024)
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#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
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/* Allow 4MB for the kernel run-time image */
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#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
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#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
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/* Other configuration settings that shouldn't have to change all that often */
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
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#endif /* __GRASSHOPPER_CONFIG_H */
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/* vim: set ts=8 noet: */
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