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e090579d0a
This commit removes definitions of CONFIG_SYS_BARGSIZE defined to be equal to CONFIG_SYS_CBSIZE in numerous configuration files. We remove such definitions in two situations: - CONFIG_SYS_CBSIZE is otherwise not defined in the board configuration file, which means the default value of CONFIG_SYS_CBSIZE == 256 applies. In this case, the default value of CONFIG_SYS_BARGSIZE == 512 (common/image.c) is suitable, as it is larger. - CONFIG_SYS_CBSIZE is defined in the board configuration file, but to a value equal or less than 512. In this case, the default value of CONFIG_SYS_BARGSIZE == 512 (common.image.c) is suitable, as it is equal or larger. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com>
279 lines
8.9 KiB
C
279 lines
8.9 KiB
C
/*
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* (C) Copyright 2011 ARM Limited
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* (C) Copyright 2010 Linaro
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* Matt Waddel, <matt.waddel@linaro.org>
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*
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* Configuration for Versatile Express. Parts were derived from other ARM
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* configurations.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __VEXPRESS_COMMON_H
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#define __VEXPRESS_COMMON_H
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/*
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* Definitions copied from linux kernel:
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* arch/arm/mach-vexpress/include/mach/motherboard.h
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*/
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#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
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/* CS register bases for the original memory map. */
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#define V2M_PA_CS0 0x40000000
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#define V2M_PA_CS1 0x44000000
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#define V2M_PA_CS2 0x48000000
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#define V2M_PA_CS3 0x4c000000
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#define V2M_PA_CS7 0x10000000
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#define V2M_PERIPH_OFFSET(x) (x << 12)
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#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
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#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
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#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
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#define V2M_BASE 0x60000000
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#define CONFIG_SYS_TEXT_BASE 0x60800000
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#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
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/* CS register bases for the extended memory map. */
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#define V2M_PA_CS0 0x08000000
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#define V2M_PA_CS1 0x0c000000
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#define V2M_PA_CS2 0x14000000
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#define V2M_PA_CS3 0x18000000
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#define V2M_PA_CS7 0x1c000000
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#define V2M_PERIPH_OFFSET(x) (x << 16)
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#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
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#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
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#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
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#define V2M_BASE 0x80000000
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#define CONFIG_SYS_TEXT_BASE 0x80800000
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#endif
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/*
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* Physical addresses, offset from V2M_PA_CS0-3
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*/
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#define V2M_NOR0 (V2M_PA_CS0)
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#define V2M_NOR1 (V2M_PA_CS1)
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#define V2M_SRAM (V2M_PA_CS2)
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#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000)
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#define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000)
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#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000)
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/* Common peripherals relative to CS7. */
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#define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
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#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
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#define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
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#define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
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#define V2M_UART0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
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#define V2M_UART1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
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#define V2M_UART2 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
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#define V2M_UART3 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
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#define V2M_WDT (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
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#define V2M_TIMER01 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
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#define V2M_TIMER23 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
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#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
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#define V2M_RTC (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
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#define V2M_CF (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
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#define V2M_CLCD (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
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#define V2M_SIZE_CS7 V2M_PERIPH_OFFSET(32)
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/* System register offsets. */
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#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
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#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
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#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
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/*
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* Configuration
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*/
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#define SYS_CFG_START (1 << 31)
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#define SYS_CFG_WRITE (1 << 30)
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#define SYS_CFG_OSC (1 << 20)
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#define SYS_CFG_VOLT (2 << 20)
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#define SYS_CFG_AMP (3 << 20)
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#define SYS_CFG_TEMP (4 << 20)
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#define SYS_CFG_RESET (5 << 20)
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#define SYS_CFG_SCC (6 << 20)
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#define SYS_CFG_MUXFPGA (7 << 20)
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#define SYS_CFG_SHUTDOWN (8 << 20)
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#define SYS_CFG_REBOOT (9 << 20)
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#define SYS_CFG_DVIMODE (11 << 20)
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#define SYS_CFG_POWER (12 << 20)
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#define SYS_CFG_SITE_MB (0 << 16)
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#define SYS_CFG_SITE_DB1 (1 << 16)
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#define SYS_CFG_SITE_DB2 (2 << 16)
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#define SYS_CFG_STACK(n) ((n) << 12)
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#define SYS_CFG_ERR (1 << 1)
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#define SYS_CFG_COMPLETE (1 << 0)
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/* Board info register */
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#define SYS_ID V2M_SYSREGS
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#define CONFIG_REVISION_TAG 1
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#define CONFIG_SYS_MEMTEST_START V2M_BASE
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#define CONFIG_SYS_MEMTEST_END 0x20000000
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_SYS_L2CACHE_OFF 1
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#define CONFIG_INITRD_TAG 1
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
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#define SCTL_BASE V2M_SYSCTL
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#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
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#define CONFIG_SYS_TIMER_RATE 1000000
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#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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/* SMSC9115 Ethernet from SMSC9118 family */
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#define CONFIG_SMC911X 1
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#define CONFIG_SMC911X_32_BIT 1
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#define CONFIG_SMC911X_BASE V2M_LAN9118
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/* PL011 Serial Configuration */
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#define CONFIG_PL011_SERIAL
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#define CONFIG_PL011_CLOCK 24000000
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#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
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(void *)CONFIG_SYS_SERIAL1}
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#define CONFIG_CONS_INDEX 0
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_SYS_SERIAL0 V2M_UART0
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#define CONFIG_SYS_SERIAL1 V2M_UART1
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#define CONFIG_ARM_PL180_MMCI
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#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
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#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
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/* BOOTP options */
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000)
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#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 2
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#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
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#define PHYS_SDRAM_2 (((unsigned int)V2M_BASE) + \
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((unsigned int)0x20000000))
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#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
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#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */
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/* additions for new relocation code */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
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#include <config_distro_defaults.h>
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/* Basic environment settings */
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#define CONFIG_BOOTCOMMAND \
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"run distro_bootcmd; " \
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"run bootflash; "
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 0) \
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func(PXE, pxe, na) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
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#define CONFIG_PLATFORM_ENV_SETTINGS \
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"loadaddr=0x80008000\0" \
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"ramdisk_addr_r=0x61000000\0" \
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"kernel_addr=0x44100000\0" \
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"ramdisk_addr=0x44800000\0" \
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"maxramdisk=0x1800000\0" \
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"pxefile_addr_r=0x88000000\0" \
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"scriptaddr=0x88000000\0" \
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"kernel_addr_r=0x80008000\0"
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#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
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#define CONFIG_PLATFORM_ENV_SETTINGS \
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"loadaddr=0xa0008000\0" \
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"ramdisk_addr_r=0x81000000\0" \
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"kernel_addr=0x0c100000\0" \
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"ramdisk_addr=0x0c800000\0" \
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"maxramdisk=0x1800000\0" \
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"pxefile_addr_r=0xa8000000\0" \
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"scriptaddr=0xa8000000\0" \
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"kernel_addr_r=0xa0008000\0"
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_PLATFORM_ENV_SETTINGS \
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BOOTENV \
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"console=ttyAMA0,38400n8\0" \
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"dram=1024M\0" \
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"root=/dev/sda1 rw\0" \
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"mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
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"24M@0x2000000(initrd)\0" \
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"flashargs=setenv bootargs root=${root} console=${console} " \
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"mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
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"devtmpfs.mount=0 vmalloc=256M\0" \
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"bootflash=run flashargs; " \
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"cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
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"bootm ${kernel_addr} ${ramdisk_addr_r}\0"
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/* FLASH and environment organization */
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#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_SIZE 0x04000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_SYS_FLASH_BASE0 V2M_NOR0
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#define CONFIG_SYS_FLASH_BASE1 V2M_NOR1
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0
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/* Timeout values in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
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/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
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#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
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#define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
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/* Room required on the stack for the environment data */
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#define CONFIG_ENV_SIZE FLASH_MAX_SECTOR_SIZE
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
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/*
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* Amount of flash used for environment:
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* We don't know which end has the small erase blocks so we use the penultimate
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* sector location for the environment
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*/
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#define CONFIG_ENV_SECT_SIZE FLASH_MAX_SECTOR_SIZE
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#define CONFIG_ENV_OVERWRITE 1
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/* Store environment at top of flash */
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#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - \
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(2 * CONFIG_ENV_SECT_SIZE))
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE1 + \
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CONFIG_ENV_OFFSET)
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#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \
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CONFIG_SYS_FLASH_BASE1 }
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_LONGHELP
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#endif /* VEXPRESS_COMMON_H */
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