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0c44229859
This patch adds generic GPIO driver framework support for Marvell SoCs. To enable GPIO driver define CONFIG_MARVELL_GPIO and for GPIO commands define CONFIG_CMD_GPIO in your board configuration file. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
75 lines
2.3 KiB
C
75 lines
2.3 KiB
C
/*
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* (C) Copyright 2011
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* eInfochips Ltd. <www.einfochips.com>
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* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
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*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef __MVGPIO_H__
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#define __MVGPIO_H__
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#include <common.h>
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#ifdef CONFIG_SHEEVA_88SV331xV5
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/*
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* GPIO Register map for SHEEVA 88SV331xV5
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*/
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struct gpio_reg {
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u32 gplr; /* Pin Level Register - 0x0000 */
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u32 pad0[2];
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u32 gpdr; /* Pin Direction Register - 0x000C */
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u32 pad1[2];
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u32 gpsr; /* Pin Output Set Register - 0x0018 */
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u32 pad2[2];
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u32 gpcr; /* Pin Output Clear Register - 0x0024 */
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u32 pad3[2];
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u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */
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u32 pad4[2];
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u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */
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u32 pad5[2];
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u32 gedr; /* Edge Detect Status Register - 0x0048 */
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u32 pad6[2];
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u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */
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u32 pad7[2];
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u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */
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u32 pad8[2];
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u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable
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Register - 0x006C */
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u32 pad9[2];
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u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable
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Register - 0x0078 */
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u32 pad10[2];
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u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable
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Register - 0x0084 */
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u32 pad11[2];
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u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable
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Register - 0x0090 */
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u32 pad12[2];
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u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */
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};
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#else
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#error "CPU core subversion not defined"
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#endif
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#endif /* __MVGPIO_H__ */
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