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401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
288 lines
7.1 KiB
C
288 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
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*/
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/*
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* Please note: there are two version of the board
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* one with NAND and the other with eMMC.
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* Both NAND and eMMC cannot be set because they share the
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* same pins (SD4)
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*/
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#include <common.h>
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#include <init.h>
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#include <net.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/global_data.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/arch/sys_proto.h>
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#include <dm.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define IMX6Q_DRIVE_STRENGTH 0x30
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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int board_mmc_get_env_dev(int devno)
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{
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return devno - 1;
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}
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#ifdef CONFIG_CMD_NAND
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static void setup_gpmi_nand(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* gate ENFC_CLK_ROOT clock first,before clk source switch */
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clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* config gpmi and bch clock to 100 MHz */
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clrsetbits_le32(&mxc_ccm->cs2cdr,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
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/* enable ENFC_CLK_ROOT clock */
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setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* enable gpmi and bch clock gating */
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setbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
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/* enable apbh clock gating */
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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}
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#endif
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_CMD_NAND
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setup_gpmi_nand();
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#endif
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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/*
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* BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
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* see Table 8-11 and Table 5-9
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* BOOT_CFG1[7] = 1 (boot from NAND)
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* BOOT_CFG1[5] = 0 - raw NAND
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* BOOT_CFG1[4] = 0 - default pad settings
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* BOOT_CFG1[3:2] = 00 - devices = 1
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* BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
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* BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
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* BOOT_CFG2[2:1] = 01 - Pages In Block = 64
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* BOOT_CFG2[0] = 0 - Reset time 12ms
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*/
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static const struct boot_mode board_boot_modes[] = {
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/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
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{"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
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{"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
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{NULL, 0},
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};
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#endif
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int board_late_init(void)
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{
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#ifdef CONFIG_CMD_BMODE
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add_board_boot_modes(board_boot_modes);
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#endif
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <spl.h>
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#include <linux/libfdt.h>
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static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_sdclk_0 = 0x00000030,
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.dram_sdclk_1 = 0x00000030,
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.dram_cas = 0x00000030,
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.dram_ras = 0x00000030,
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.dram_reset = 0x00000030,
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.dram_sdcke0 = 0x00000030,
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.dram_sdcke1 = 0x00000030,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = 0x00000030,
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.dram_sdodt1 = 0x00000030,
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.dram_sdqs0 = 0x00000030,
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.dram_sdqs1 = 0x00000030,
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.dram_sdqs2 = 0x00000030,
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.dram_sdqs3 = 0x00000030,
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.dram_sdqs4 = 0x00000030,
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.dram_sdqs5 = 0x00000030,
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.dram_sdqs6 = 0x00000030,
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.dram_sdqs7 = 0x00000030,
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.dram_dqm0 = 0x00000030,
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.dram_dqm1 = 0x00000030,
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.dram_dqm2 = 0x00000030,
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.dram_dqm3 = 0x00000030,
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.dram_dqm4 = 0x00000030,
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.dram_dqm5 = 0x00000030,
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.dram_dqm6 = 0x00000030,
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.dram_dqm7 = 0x00000030,
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};
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static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
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.grp_ddr_type = 0x000C0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = IMX6Q_DRIVE_STRENGTH,
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.grp_ctlds = IMX6Q_DRIVE_STRENGTH,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = IMX6Q_DRIVE_STRENGTH,
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.grp_b1ds = IMX6Q_DRIVE_STRENGTH,
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.grp_b2ds = IMX6Q_DRIVE_STRENGTH,
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.grp_b3ds = IMX6Q_DRIVE_STRENGTH,
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.grp_b4ds = IMX6Q_DRIVE_STRENGTH,
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.grp_b5ds = IMX6Q_DRIVE_STRENGTH,
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.grp_b6ds = IMX6Q_DRIVE_STRENGTH,
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.grp_b7ds = IMX6Q_DRIVE_STRENGTH,
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};
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static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00140014,
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.p0_mpwldectrl1 = 0x000A0015,
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.p1_mpwldectrl0 = 0x000A001E,
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.p1_mpwldectrl1 = 0x000A0015,
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.p0_mpdgctrl0 = 0x43080314,
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.p0_mpdgctrl1 = 0x02680300,
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.p1_mpdgctrl0 = 0x430C0318,
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.p1_mpdgctrl1 = 0x03000254,
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.p0_mprddlctl = 0x3A323234,
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.p1_mprddlctl = 0x3E3C3242,
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.p0_mpwrdlctl = 0x2A2E3632,
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.p1_mpwrdlctl = 0x3C323E34,
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};
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static struct mx6_ddr3_cfg mem_ddr = {
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.mem_speed = 1600,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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.SRT = 1,
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC03, &ccm->CCGR1);
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writel(0x0FFFC000, &ccm->CCGR2);
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writel(0x3FF00000, &ccm->CCGR3);
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writel(0x00FFF300, &ccm->CCGR4);
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writel(0x0F0000C3, &ccm->CCGR5);
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writel(0x000003FF, &ccm->CCGR6);
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}
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static void spl_dram_init(void)
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{
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struct mx6_ddr_sysinfo sysinfo = {
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/* width of data bus:0=16,1=32,2=64 */
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.dsize = 2,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32, /* 32Gb per CS */
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/* single chip select */
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
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.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
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.walat = 1, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.ddr_type = DDR_TYPE_DDR3,
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.refsel = 1, /* Refresh cycles at 32KHz */
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.refr = 7, /* 8 refresh commands per refresh cycle */
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};
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mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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spl_boot_list[0] = spl_boot_device();
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printf("Boot device %x\n", spl_boot_list[0]);
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switch (spl_boot_list[0]) {
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case BOOT_DEVICE_SPI:
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spl_boot_list[1] = BOOT_DEVICE_UART;
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break;
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case BOOT_DEVICE_MMC1:
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spl_boot_list[1] = BOOT_DEVICE_SPI;
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spl_boot_list[2] = BOOT_DEVICE_UART;
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break;
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default:
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printf("Boot device %x\n", spl_boot_list[0]);
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}
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}
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void board_init_f(ulong dummy)
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{
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/* setup clock gating */
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ccgr_init();
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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/* setup AXI */
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gpr_init();
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/* setup GP timer */
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timer_init();
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/* DDR initialization */
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spl_dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/* Enable device tree and early DM support*/
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spl_early_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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}
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/*
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* Manually probe the SPI bus devices, as this does not happen when the
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* SPI Flash is probed, which then fails to find the bus.
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*/
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void spl_board_init(void)
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{
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struct udevice *udev;
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int ret = uclass_get_device_by_name(UCLASS_SPI, "spi@2008000", &udev);
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if (ret) {
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printf("SPI bus probe failed, err = %d\n", ret);
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};
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}
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#endif
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