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29795302b9
Bit 15 in SAR register specifies if TCLK is running at 200 MHz or 250 MHz. Use this information instead of manual configuration in every board file. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
69 lines
1.6 KiB
C
69 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*/
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#ifndef _CONFIG_DB_88F6820_AMC_H
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#define _CONFIG_DB_88F6820_AMC_H
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/*
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* High Level Configuration Options (easy to change)
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*/
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/* USB/EHCI configuration */
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#define CONFIG_EHCI_IS_TDI
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/* Environment in SPI NOR flash */
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
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/* PCIe support */
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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/* NAND */
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* Keep device tree and initrd in lower memory so the kernel can access them */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0x10000000\0" \
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"initrd_high=0x10000000\0"
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/* SPL */
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/*
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* Select the boot device here
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*
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* Currently supported are:
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* SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
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*
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* MMC is not populated on this board.
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* NAND support may be added in the future.
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*/
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#define SPL_BOOT_SPI_NOR_FLASH 1
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#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
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/* Defines for SPL */
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#define CONFIG_SPL_SIZE (140 << 10)
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#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
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#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MALLOC_SIMPLE
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#endif
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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/*
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* mv-common.h should be defined after CMD configs since it used them
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* to enable certain macros
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*/
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#include "mv-common.h"
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#undef CONFIG_SYS_MAXARGS
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#define CONFIG_SYS_MAXARGS 96
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#endif /* _CONFIG_DB_88F6820_AMC_H */
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