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2c2ab3d495
Initial support for PXs3 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
183 lines
5.1 KiB
Plaintext
183 lines
5.1 KiB
Plaintext
U-Boot for UniPhier SoC family
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==============================
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Recommended toolchains
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----------------------
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The UniPhir platform is well tested with Linaro toolchanis.
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You can download pre-built toolchains from:
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http://www.linaro.org/downloads/
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Compile the source
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------------------
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sLD3 reference board:
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$ make uniphier_sld3_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabihf-
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LD4 reference board:
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$ make uniphier_ld4_sld8_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabihf-
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sLD8 reference board:
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$ make uniphier_ld4_sld8_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-sld8-ref
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Pro4 reference board:
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$ make uniphier_pro4_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabihf-
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Pro4 Ace board:
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$ make uniphier_pro4_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-ace
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Pro4 Sanji board:
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$ make uniphier_pro4_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-sanji
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Pro5 4KBOX Board:
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$ make uniphier_pxs2_ld6b_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro5-4kbox
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PXs2 Gentil board:
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$ make uniphier_pxs2_ld6b_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-gentil
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PXs2 Vodka board:
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$ make uniphier_pxs2_ld6b_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabihf-
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LD6b reference board:
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$ make uniphier_pxs2_ld6b_defconfig
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$ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-ld6b-ref
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LD11 reference board:
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$ make uniphier_ld11_defconfig
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$ make CROSS_COMPILE=aarch64-linux-gnu-
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LD20 reference board:
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$ make uniphier_ld20_defconfig
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$ make CROSS_COMPILE=aarch64-linux-gnu-
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PXs3 reference board:
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$ make uniphier_v8_defconfig
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$ make CROSS_COMPILE=aarch64-linux-gnu- DEVICE_TREE=uniphier-pxs3-ref
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You may wish to change the "CROSS_COMPILE=..." to use your favorite compiler.
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Burn U-Boot images to NAND
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--------------------------
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Write the following to the NAND device:
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- spl/u-boot-spl.bin at the offset address 0x00000000
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- u-boot.bin at the offset address 0x00010000
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or
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- u-boot-with-spl.bin at the offset address 0x00000000
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If a TFTP server is available, the images can be easily updated.
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Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory,
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and then run the following command at the U-Boot command line:
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=> run nandupdate
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Burn U-Boot images to eMMC
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--------------------------
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Write the following to the Boot partition 1 of the eMMC device:
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- spl/u-boot-spl.bin at the offset address 0x00000000
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- u-boot.bin at the offset address 0x00010000
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or
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- u-boot-with-spl.bin at the offset address 0x00000000
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If a TFTP server is available, the images can be easily updated.
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Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory,
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and then run the following command at the U-Boot command line:
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=> run emmcupdate
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UniPhier specific commands
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--------------------------
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- pinmon (enabled by CONFIG_CMD_PINMON)
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shows the boot mode pins that has been latched at the power-on reset
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- ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP)
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shows the DDR PHY parameters set by the PHY training
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- ddrmphy (enabled by CONFIG_CMD_DDRMPHY_DUMP)
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shows the DDR Multi PHY parameters set by the PHY training
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Supported devices
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-----------------
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- UART (on-chip)
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- NAND
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- SD/eMMC
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- USB 2.0 (EHCI)
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- USB 3.0 (xHCI)
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- GPIO
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- LAN (on-board SMSC9118)
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- I2C
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- EEPROM (connected to the on-board I2C bus)
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- Support card (SRAM, NOR flash, some peripherals)
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Micro Support Card
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------------------
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The recommended bit switch settings are as follows:
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SW2 OFF(1)/ON(0) Description
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------------------------------------------
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bit 1 <---- BKSZ[0]
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bit 2 ----> BKSZ[1]
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bit 3 <---- SoC Bus Width 16/32
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bit 4 <---- SERIAL_SEL[0]
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bit 5 ----> SERIAL_SEL[1]
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bit 6 ----> BOOTSWAP_EN
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bit 7 <---- CS1/CS5
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bit 8 <---- SOC_SERIAL_DISABLE
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SW8 OFF(1)/ON(0) Description
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------------------------------------------
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bit 1 <---- CS1_SPLIT
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bit 2 <---- CASE9_ON
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bit 3 <---- CASE10_ON
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bit 4 Don't Care Reserve
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bit 5 Don't Care Reserve
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bit 6 Don't Care Reserve
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bit 7 ----> BURST_EN
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bit 8 ----> FLASHBUS32_16
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The BKSZ[1:0] specifies the address range of memory slot and peripherals
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as follows:
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BKSZ Description RAM slot Peripherals
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--------------------------------------------------------------------
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0b00 15MB RAM / 1MB Peri 00000000-00efffff 00f00000-00ffffff
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0b01 31MB RAM / 1MB Peri 00000000-01efffff 01f00000-01ffffff
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0b10 64MB RAM / 1MB Peri 00000000-03efffff 03f00000-03ffffff
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0b11 127MB RAM / 1MB Peri 00000000-07efffff 07f00000-07ffffff
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Set BSKZ[1:0] to 0b01 for U-Boot.
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This mode is the most handy because EA[24] is always supported by the save pin
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mode of the system bus. On the other hand, EA[25] is not supported for some
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newer SoCs. Even if it is, EA[25] is not connected on most of the boards.
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--
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Masahiro Yamada <yamada.masahiro@socionext.com>
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Oct. 2016
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