mirror of
https://github.com/u-boot/u-boot.git
synced 2024-12-12 06:03:30 +08:00
55ca747f66
There is no need for RISCV_NDS_CACHE config to control cache switches. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
49 lines
1.3 KiB
Plaintext
49 lines
1.3 KiB
Plaintext
#
|
|
# Cache controllers
|
|
#
|
|
|
|
menu "Cache Controller drivers"
|
|
|
|
config CACHE
|
|
bool "Enable Driver Model for Cache controllers"
|
|
depends on DM
|
|
help
|
|
Enable driver model for cache controllers that are found on
|
|
most CPU's. Cache is memory that the CPU can access directly and
|
|
is usually located on the same chip. This uclass can be used for
|
|
configuring settings that be found from a device tree file.
|
|
|
|
config L2X0_CACHE
|
|
tristate "PL310 cache driver"
|
|
select CACHE
|
|
depends on ARM
|
|
help
|
|
This driver is for the PL310 cache controller commonly found on
|
|
ARMv7(32-bit) devices. The driver configures the cache settings
|
|
found in the device tree.
|
|
|
|
config V5L2_CACHE
|
|
bool "Andes V5L2 cache driver"
|
|
select CACHE
|
|
help
|
|
Support Andes V5L2 cache controller in AE350 platform.
|
|
It will configure tag and data ram timing control from the
|
|
device tree and enable L2 cache.
|
|
|
|
config NCORE_CACHE
|
|
bool "Arteris Ncore cache coherent unit driver"
|
|
select CACHE
|
|
help
|
|
This driver is for the Arteris Ncore cache coherent unit (CCU)
|
|
controller. The driver initializes cache directories and coherent
|
|
agent interfaces.
|
|
|
|
config SIFIVE_CCACHE
|
|
bool "SiFive composable cache"
|
|
select CACHE
|
|
help
|
|
This driver is for SiFive Composable L2/L3 cache. It enables cache
|
|
ways of composable cache.
|
|
|
|
endmenu
|