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c904a0b762
Also change back SYS_MEMTEST_END to 0x00f00000. 0xe00000 was wrong and introduced due to the global Kconfig migration of this option in u-boot. CC: Heiko Schocher <hs@denx.de> CC: Tom Rini <trini@konsulko.com> Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com>
59 lines
1.6 KiB
C
59 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2012
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* Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
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* Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_HOSTNAME "kmcoge5ne"
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#define CONFIG_NAND_ECC_BCH
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#define CONFIG_NAND_KMETER1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
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#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
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#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
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/* include common defines/options for all Keymile boards */
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#include "km/keymile-common.h"
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#include "km/km-powerpc.h"
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#include "km/km-mpc83xx.h"
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#include "km/km-mpc8360.h"
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/*
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* System Clock Setup
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*/
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#define CONFIG_83XX_CLKIN 66000000
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#define CONFIG_SYS_CLK_FREQ 66000000
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#define CONFIG_83XX_PCICLK 66000000
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/**
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* KMCOGE5NE has 512 MB RAM
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*/
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#define CONFIG_SYS_DDR_CS0_CONFIG (\
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CSCONFIG_EN | \
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CSCONFIG_AP | \
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CSCONFIG_ODT_WR_ONLY_CURRENT | \
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CSCONFIG_BANK_BIT_3 | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10)
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/*
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* BFTIC3 on the local bus CS4
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*/
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#define CONFIG_SYS_BFTIC3_BASE 0xB0000000
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#define CONFIG_SYS_BFTIC3_SIZE 256
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/* enable POST tests */
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#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
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#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
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#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
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#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
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#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
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#endif /* CONFIG */
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