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8aa1a2d115
- remove all references to CONFIG_INIT_CRITICAL for ARM based boards - introduce two new configuration options instead: CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT
163 lines
5.3 KiB
C
163 lines
5.3 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* 2004 (c) MontaVista Software, Inc.
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*
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* Configuation settings for the Intel Assabet board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#undef DEBUG
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_SA1110 1 /* This is an SA1100 CPU */
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#define CONFIG_ASSABET 1 /* on an Intel Assabet Board */
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#undef CONFIG_USE_IRQ
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_GBL_DATA_SIZE 128 /* size rsrvd for initial data */
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/*
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* Hardware drivers
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*/
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#define CONFIG_DRIVER_LAN91C96 /* we have an SMC9194 on-board */
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#define CONFIG_LAN91C96_BASE 0x18000000
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/*
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* select serial console configuration
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*/
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#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on Intel Assabet */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
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#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp"
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#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
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#define CFG_AUTOLOAD "n" /* No autoload */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "Intel Assabet # " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */
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#undef CFG_CLKS_IN_HZ
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#define CFG_LOAD_ADDR 0xc0000000 /* default load address */
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#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CFG_CPUSPEED 0x0a /* set core clock to 206MHz */
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
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#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
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#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
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#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
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#if CFG_MONITOR_BASE < CFG_FLASH_BASE
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#define CFG_RAMSTART
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#endif
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CFG_FLASH_BASE PHYS_FLASH_1
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#define CFG_FLASH_SIZE PHYS_FLASH_SIZE
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#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
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#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
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#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
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#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
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#undef CFG_FLASH_PROTECTION
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
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#define CFG_ENV_IS_IN_FLASH 1
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#if defined(CFG_ENV_IS_IN_FLASH)
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#define CFG_ENV_IN_OWN_SECTOR 1
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#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
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#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE
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#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
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#endif
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#endif /* __CONFIG_H */
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