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2471111d35
Enable ranges in mii command, e.g. mii read 0-1f 0 or mii read 4-7 18-1a. Also add mii dump subcommand for pretty-printing standard regs 0-5. * Patch by Stephen Williams, 16 April 2004: fix typo in JSE.h; update MAINTAINERS
305 lines
10 KiB
C
305 lines
10 KiB
C
/*
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* (C) Copyright 2003 Picture Elements, Inc.
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* Stephen Williams <steve@icarus.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options for the JSE board
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* (Theoretically easy to change, but the board is fixed.)
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*/
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#define CONFIG_JSE 1
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/* JSE has a PPC405GPr */
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#define CONFIG_405GP 1
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/* ... which is a 4xxx series */
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#define CONFIG_4xx 1
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/* ... with a 33MHz OSC. connected to the SysCLK input */
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#define CONFIG_SYS_CLK_FREQ 33333333
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/* ... with on-chip memory here (4KBytes) */
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#define CFG_OCM_DATA_ADDR 0xF4000000
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#define CFG_OCM_DATA_SIZE 0x00001000
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/* Do not set up locked dcache as init ram. */
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#undef CFG_INIT_DCACHE_CS
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/* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
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#define CONFIG_SYSTEMACE 1
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#define CFG_SYSTEMACE_BASE 0xf0000000
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#define CONFIG_DOS_PARTITION 1
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/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
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#define CFG_TEMP_STACK_OCM 1
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/* ... place INIT RAM in the OCM address */
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# define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR
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/* ... give it the whole init ram */
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# define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE
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/* ... Shave a bit off the end for global data */
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# define CFG_GBL_DATA_SIZE 128
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# define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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/* ... and place the stack pointer at the top of what's left. */
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# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/* Enable board_pre_init function */
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#define CONFIG_BOARD_PRE_INIT 1
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#define CONFIG_BOARD_EARLY_INIT_F 1
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/* Disable post-clk setup init function */
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#undef CONFIG_BOARD_POSTCLK_INIT
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/* Disable call to post_init_f: late init function. */
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#undef CONFIG_POST
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/* Enable DRAM test. */
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#define CFG_DRAM_TEST 1
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/* Enable misc_init_r function. */
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#define CONFIG_MISC_INIT_R 1
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/* JSE has EEPROM chips that are good for environment. */
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#undef CFG_ENV_IS_IN_NVRAM
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#undef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_IS_IN_EEPROM 1
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#undef CFG_ENV_IS_NOWHERE
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/* This is the 7bit address of the device, not including P. */
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#define CFG_I2C_EEPROM_ADDR 0x50
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/* After the device address, need one more address byte. */
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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/* The EEPROM is 512 bytes. */
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#define CFG_EEPROM_SIZE 512
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/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
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#define CFG_EEPROM_PAGE_WRITE_BITS 4
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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/* Put the environment in the second half. */
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#define CFG_ENV_OFFSET 0x00
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#define CFG_ENV_SIZE 512
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/* The JSE connects UART1 to the console tap connector. */
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#define CONFIG_UART1_CONSOLE 1
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/* Set console baudrate to 9600 */
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#define CONFIG_BAUDRATE 9600
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/* Size (bytes) of interrupt driven serial port buffer.
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* Set to 0 to use polling instead of interrupts.
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* Setting to 0 will also disable RTS/CTS handshaking.
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*/
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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/*
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* Configuration related to auto-boot.
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*
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* CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait
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* before resorting to autoboot. This value can be overridden by the
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* bootdelay environment variable.
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*
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* CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the
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* user that an autoboot will happen.
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*
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* CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will
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* execute to boot the JSE. This loads the uimage and initrd.img files
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* from CompactFlash into memory, then boots them from memory.
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*
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* CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get
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* it going on the JSE.
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*/
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_BOOTARGS "root=/dev/ram0 init=/linuxrc rw"
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#define CONFIG_BOOTCOMMAND "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 1 /* PHY address */
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_PCI | \
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CFG_CMD_IRQ | \
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CFG_CMD_FLASH | \
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CFG_CMD_NET | \
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CFG_CMD_DHCP | \
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CFG_CMD_PING | \
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CFG_CMD_MII | \
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CFG_CMD_EEPROM | \
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CFG_CMD_FAT | \
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CFG_CMD_ELF )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/* watchdog disabled */
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#undef CONFIG_WATCHDOG
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/* SPD EEPROM (sdram speed config) disabled */
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#undef CONFIG_SPD_EEPROM
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#undef SPD_EEPROM_ADDRESS
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_HUSH_PARSER /* use "hush" command parser */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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/*
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* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
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* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
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* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
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* The Linux BASE_BAUD define should match this configuration.
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* baseBaud = cpuClock/(uartDivisor*16)
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* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
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* set Linux BASE_BAUD to 403200.
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*/
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#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
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#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
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#define CFG_BASE_BAUD 691200
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/* The following table includes the supported baudrates */
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#undef CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
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#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
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#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
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#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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/*-----------------------------------------------------------------------
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* External peripheral base address
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#undef CONFIG_IDE_RESET /* no reset for ide supported */
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#define CFG_KEY_REG_BASE_ADDR 0xF0100000
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#define CFG_IR_REG_BASE_ADDR 0xF0200000
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#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFFF80000
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */
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#define CFG_CACHELINE_SIZE 32 /* ... */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
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/* Configuration Port location */
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#define CONFIG_PORT_ADDR 0xF0000500
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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#endif /* __CONFIG_H */
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