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https://github.com/u-boot/u-boot.git
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b54d32b40d
Add support for Intel K3 strata flash. * Some cleanup * Patch by Thomas Brand, 10 Jun 2004: Fix "loads" command on DK1S10 board
465 lines
16 KiB
C
465 lines
16 KiB
C
/*
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* A collection of structures, addresses, and values associated with
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* the Motorola 860T FADS board. Copied from the MBX stuff.
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* Magnus Damm added defines for 8xxrom and extended bd_info.
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* Helmut Buchsbaum added bitvalues for BCSRx
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*
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
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*/
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/*
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* 1999-nov-26: The FADS is using the following physical memorymap:
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*
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* ff020000 -> ff02ffff : pcmcia io remapping
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* ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot
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* ff000000 -> ff00ffff : IMAP internal in the cpu
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* e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia
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* fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot
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* 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
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*/
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#define CFG_PCMCIA_IO_ADDR 0xff020000
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#define CFG_PCMCIA_IO_SIZE 0x10000
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#define CFG_PCMCIA_MEM_ADDR 0xe0000000
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#define CFG_PCMCIA_MEM_SIZE 0x10000
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#define CFG_IMMR 0xFF000000
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#define CFG_SDRAM_SIZE (4<<20) /* standard FADS has 4M */
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x02800000
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#define BCSR_ADDR ((uint) 0xff010000)
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#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
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#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
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#define CONFIG_VIDEO 1 /* To enable video controller support */
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#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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/*Now included by CFG_CMD_PCMCIA */
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/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */
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/* Video related */
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#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
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#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
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#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */
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#define CONFIG_VIDEO_SIZE (2*1024*1024)
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/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
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/* Wireless 56Khz 4PPM keyboard on SMCx */
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/*#define CONFIG_KEYBOARD 1 */
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#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC823 1
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#define CONFIG_MPC823FADS 1
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#define CONFIG_FADS 1
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 115200
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/* Set the CPU speed to 50Mhz on the FADS */
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#if 0
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#define MPC8XX_FACT 10 /* Multiply by 10 */
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#define MPC8XX_XIN 5000000 /* 5 MHz in */
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#else
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#define MPC8XX_FACT 10 /* Multiply by 10 */
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#define MPC8XX_XIN 5000000 /* 5 MHz in */
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#define CFG_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */
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#endif
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#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#if 1
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#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
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#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */
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#define CONFIG_BOOTARGS ""
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#define CONFIG_BOOTCOMMAND \
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"bootp ;" \
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"setenv bootargs console=tty0 console=ttyS0 " \
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"root=/dev/nfs nfsroot=$(serverip):$(rootpath) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off ;" \
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"bootm"
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#else
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#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT ":>" /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
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#define CFG_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */
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#define CFG_LOAD_ADDR 0x00100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR_SIZE ((uint)(64 * 1024))
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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* Also NOTE that it doesn't mean SDRAM - it means MEMORY.
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*/
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#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
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#if 0
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
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#endif
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer *
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* interrupt status bit - leave PLL multiplication factor unchanged !
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*/
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR (SCCR_TBS | \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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#define CFG_DER 0
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/* Because of the way the 860 starts up and assigns CS0 the
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* entire address space, we have to set the memory controller
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* differently. Normally, you write the option register
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* first, and then enable the chip select by writing the
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* base register. For CS0, you must write the base register
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* first, followed by the option register.
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*/
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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/* the other CS:s are determined by looking at parameters in BCSRx */
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#define BCSR_SIZE ((uint)(64 * 1024))
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#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
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#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
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#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
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/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
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/* BCSRx - Board Control and Status Registers */
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#define CFG_OR1_REMAP CFG_OR0_REMAP
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#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
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#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
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/*
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* Memory Periodic Timer Prescaler
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*/
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/* periodic timer for refresh */
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#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
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/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
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#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
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#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
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/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
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#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
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#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
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/*
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* MAMR settings for SDRAM
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*/
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/* 8 column SDRAM */
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#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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/* 9 column SDRAM */
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#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
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#define CFG_MAMR 0x13a01114
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/* values according to the manual */
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#define BCSR0 ((uint) (BCSR_ADDR + 00))
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#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
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#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
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#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
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#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
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/* FADS bitvalues by Helmut Buchsbaum
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* see MPC8xxADS User's Manual for a proper description
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* of the following structures
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*/
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#define BCSR0_ERB ((uint)0x80000000)
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#define BCSR0_IP ((uint)0x40000000)
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#define BCSR0_BDIS ((uint)0x10000000)
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#define BCSR0_BPS_MASK ((uint)0x0C000000)
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#define BCSR0_ISB_MASK ((uint)0x01800000)
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#define BCSR0_DBGC_MASK ((uint)0x00600000)
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#define BCSR0_DBPC_MASK ((uint)0x00180000)
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#define BCSR0_EBDF_MASK ((uint)0x00060000)
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#define BCSR1_FLASH_EN ((uint)0x80000000)
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#define BCSR1_DRAM_EN ((uint)0x40000000)
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#define BCSR1_ETHEN ((uint)0x20000000)
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#define BCSR1_IRDEN ((uint)0x10000000)
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#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
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#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
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#define BCSR1_BCSR_EN ((uint)0x02000000)
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#define BCSR1_RS232EN_1 ((uint)0x01000000)
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#define BCSR1_PCCEN ((uint)0x00800000)
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#define BCSR1_PCCVCC0 ((uint)0x00400000)
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#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
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#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
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#define BCSR1_RS232EN_2 ((uint)0x00040000)
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#define BCSR1_SDRAM_EN ((uint)0x00020000)
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#define BCSR1_PCCVCC1 ((uint)0x00010000)
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#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
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#define BCSR2_FLASH_PD_SHIFT 28
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#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
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#define BCSR2_DRAM_PD_SHIFT 23
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#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
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#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
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#define BCSR3_DBID_MASK ((ushort)0x3800)
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#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
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#define BCSR3_BREVNR0 ((ushort)0x0080)
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#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
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#define BCSR3_BREVN1 ((ushort)0x0008)
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#define BCSR3_BREVN2_MASK ((ushort)0x0003)
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#define BCSR4_ETHLOOP ((uint)0x80000000)
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#define BCSR4_TFPLDL ((uint)0x40000000)
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#define BCSR4_TPSQEL ((uint)0x20000000)
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#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
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#ifdef CONFIG_MPC823
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#define BCSR4_USB_EN ((uint)0x08000000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC860SAR
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#define BCSR4_UTOPIA_EN ((uint)0x08000000)
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#endif /* CONFIG_MPC860SAR */
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#ifdef CONFIG_MPC860T
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#define BCSR4_FETH_EN ((uint)0x08000000)
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#endif /* CONFIG_MPC860T */
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#ifdef CONFIG_MPC823
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#define BCSR4_USB_SPEED ((uint)0x04000000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC860T
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#define BCSR4_FETHCFG0 ((uint)0x04000000)
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#endif /* CONFIG_MPC860T */
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#ifdef CONFIG_MPC823
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#define BCSR4_VCCO ((uint)0x02000000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC860T
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#define BCSR4_FETHFDE ((uint)0x02000000)
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#endif /* CONFIG_MPC860T */
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#ifdef CONFIG_MPC823
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#define BCSR4_VIDEO_ON ((uint)0x00800000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC823
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#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
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#endif /* CONFIG_MPC823 */
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#ifdef CONFIG_MPC860T
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#define BCSR4_FETHCFG1 ((uint)0x00400000)
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#endif /* CONFIG_MPC860T */
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#ifdef CONFIG_MPC823
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#define BCSR4_VIDEO_RST ((uint)0x00200000)
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#endif /* CONFIG_MPC823 */
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|
#ifdef CONFIG_MPC860T
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|
#define BCSR4_FETHRST ((uint)0x00200000)
|
|
#endif /* CONFIG_MPC860T */
|
|
#ifdef CONFIG_MPC823
|
|
#define BCSR4_MODEM_EN ((uint)0x00100000)
|
|
#endif /* CONFIG_MPC823 */
|
|
#ifdef CONFIG_MPC823
|
|
#define BCSR4_DATA_VOICE ((uint)0x00080000)
|
|
#endif /* CONFIG_MPC823 */
|
|
#ifdef CONFIG_MPC850
|
|
#define BCSR4_DATA_VOICE ((uint)0x00080000)
|
|
#endif /* CONFIG_MPC850 */
|
|
|
|
#define CONFIG_DRAM_50MHZ 1
|
|
#define CONFIG_SDRAM_50MHZ
|
|
|
|
/* We don't use the 8259.
|
|
*/
|
|
#define NR_8259_INTS 0
|
|
|
|
/* Machine type
|
|
*/
|
|
#define _MACH_8xx (_MACH_fads)
|
|
|
|
/*
|
|
* MPC8xx CPM Options
|
|
*/
|
|
#define CONFIG_SCC_ENET 1
|
|
#define CONFIG_SCC2_ENET 1
|
|
#undef CONFIG_FEC_ENET
|
|
#undef CONFIG_CPM_IIC
|
|
#undef CONFIG_UCODE_PATCH
|
|
|
|
#define CONFIG_DISK_SPINUP_TIME 1000000
|
|
|
|
/* PCMCIA configuration */
|
|
|
|
#define PCMCIA_MAX_SLOTS 1
|
|
|
|
#ifdef CONFIG_MPC860
|
|
#define PCMCIA_SLOT_A 1
|
|
#endif
|
|
|
|
#define CFG_DAUGHTERBOARD
|
|
|
|
#endif /* __CONFIG_H */
|