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57faca19a8
OHCI has a known limitation of allowing only 32-bit DMA buffer addresses, so we have a lot of u32 variables around, which are assigned to pointers and vice versa. This obviously creates issues with 64-bit systems, so the compiler complains here and there. To allow compilation for 64-bit boards which use only memory below 4GB anyway (and to avoid more invasive fixes), adjust some casts and types and assume that the EDs and TDs are all located in the lower 4GB. This fixes compilation of the OHCI driver for the Pine64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
422 lines
12 KiB
C
422 lines
12 KiB
C
/*
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* URB OHCI HCD (Host Controller Driver) for USB.
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*
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* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
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* (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
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*
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* usb-ohci.h
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*/
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/*
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* e.g. PCI controllers need this
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*/
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#include <asm/io.h>
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#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
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# define ohci_readl(a) __swap_32(readl(a))
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# define ohci_writel(v, a) writel(__swap_32(v), a)
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#else
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# define ohci_readl(a) readl(a)
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# define ohci_writel(v, a) writel(v, a)
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#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
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#if ARCH_DMA_MINALIGN > 16
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#define ED_ALIGNMENT ARCH_DMA_MINALIGN
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#else
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#define ED_ALIGNMENT 16
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#endif
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#if defined CONFIG_DM_USB && ARCH_DMA_MINALIGN > 32
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#define TD_ALIGNMENT ARCH_DMA_MINALIGN
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#else
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#define TD_ALIGNMENT 32
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#endif
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/* functions for doing board or CPU specific setup/cleanup */
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int usb_board_stop(void);
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int usb_cpu_init(void);
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int usb_cpu_stop(void);
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int usb_cpu_init_fail(void);
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/* ED States */
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#define ED_NEW 0x00
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#define ED_UNLINK 0x01
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#define ED_OPER 0x02
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#define ED_DEL 0x04
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#define ED_URB_DEL 0x08
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/* usb_ohci_ed */
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struct ed {
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__u32 hwINFO;
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__u32 hwTailP;
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__u32 hwHeadP;
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__u32 hwNextED;
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struct ed *ed_prev;
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__u8 int_period;
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__u8 int_branch;
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__u8 int_load;
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__u8 int_interval;
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__u8 state;
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__u8 type;
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__u16 last_iso;
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struct ed *ed_rm_list;
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struct usb_device *usb_dev;
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void *purb;
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__u32 unused[2];
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} __attribute__((aligned(ED_ALIGNMENT)));
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typedef struct ed ed_t;
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/* TD info field */
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#define TD_CC 0xf0000000
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#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
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#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
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#define TD_EC 0x0C000000
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#define TD_T 0x03000000
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#define TD_T_DATA0 0x02000000
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#define TD_T_DATA1 0x03000000
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#define TD_T_TOGGLE 0x00000000
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#define TD_R 0x00040000
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#define TD_DI 0x00E00000
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#define TD_DI_SET(X) (((X) & 0x07)<< 21)
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#define TD_DP 0x00180000
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#define TD_DP_SETUP 0x00000000
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#define TD_DP_IN 0x00100000
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#define TD_DP_OUT 0x00080000
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#define TD_ISO 0x00010000
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#define TD_DEL 0x00020000
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/* CC Codes */
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#define TD_CC_NOERROR 0x00
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#define TD_CC_CRC 0x01
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#define TD_CC_BITSTUFFING 0x02
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#define TD_CC_DATATOGGLEM 0x03
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#define TD_CC_STALL 0x04
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#define TD_DEVNOTRESP 0x05
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#define TD_PIDCHECKFAIL 0x06
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#define TD_UNEXPECTEDPID 0x07
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#define TD_DATAOVERRUN 0x08
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#define TD_DATAUNDERRUN 0x09
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#define TD_BUFFEROVERRUN 0x0C
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#define TD_BUFFERUNDERRUN 0x0D
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#define TD_NOTACCESSED 0x0F
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#define MAXPSW 1
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struct td {
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__u32 hwINFO;
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__u32 hwCBP; /* Current Buffer Pointer */
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__u32 hwNextTD; /* Next TD Pointer */
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__u32 hwBE; /* Memory Buffer End Pointer */
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/* #ifndef CONFIG_MPC5200 /\* this seems wrong *\/ */
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__u16 hwPSW[MAXPSW];
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/* #endif */
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__u8 unused;
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__u8 index;
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struct ed *ed;
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struct td *next_dl_td;
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struct usb_device *usb_dev;
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int transfer_len;
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__u32 data;
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__u32 unused2[2];
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} __attribute__((aligned(TD_ALIGNMENT)));
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typedef struct td td_t;
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#define OHCI_ED_SKIP (1 << 14)
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/*
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* The HCCA (Host Controller Communications Area) is a 256 byte
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* structure defined in the OHCI spec. that the host controller is
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* told the base address of. It must be 256-byte aligned.
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*/
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#define NUM_INTS 32 /* part of the OHCI standard */
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struct ohci_hcca {
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__u32 int_table[NUM_INTS]; /* Interrupt ED table */
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#if defined(CONFIG_MPC5200)
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__u16 pad1; /* set to 0 on each frame_no change */
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__u16 frame_no; /* current frame number */
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#else
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__u16 frame_no; /* current frame number */
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__u16 pad1; /* set to 0 on each frame_no change */
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#endif
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__u32 done_head; /* info returned for an interrupt */
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u8 reserved_for_hc[116];
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} __attribute__((aligned(256)));
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/*
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* Maximum number of root hub ports.
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*/
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#ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
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# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
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#endif
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/*
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* This is the structure of the OHCI controller's memory mapped I/O
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* region. This is Memory Mapped I/O. You must use the ohci_readl() and
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* ohci_writel() macros defined in this file to access these!!
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*/
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struct ohci_regs {
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/* control and status registers */
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__u32 revision;
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__u32 control;
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__u32 cmdstatus;
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__u32 intrstatus;
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__u32 intrenable;
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__u32 intrdisable;
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/* memory pointers */
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__u32 hcca;
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__u32 ed_periodcurrent;
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__u32 ed_controlhead;
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__u32 ed_controlcurrent;
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__u32 ed_bulkhead;
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__u32 ed_bulkcurrent;
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__u32 donehead;
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/* frame counters */
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__u32 fminterval;
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__u32 fmremaining;
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__u32 fmnumber;
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__u32 periodicstart;
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__u32 lsthresh;
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/* Root hub ports */
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struct ohci_roothub_regs {
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__u32 a;
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__u32 b;
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__u32 status;
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__u32 portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS];
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} roothub;
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} __attribute__((aligned(32)));
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/* Some EHCI controls */
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#define EHCI_USBCMD_OFF 0x20
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#define EHCI_USBCMD_HCRESET (1 << 1)
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/* OHCI CONTROL AND STATUS REGISTER MASKS */
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/*
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* HcControl (control) register masks
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*/
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#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
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#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
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#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
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#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
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#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
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#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
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#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
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#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
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#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
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/* pre-shifted values for HCFS */
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# define OHCI_USB_RESET (0 << 6)
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# define OHCI_USB_RESUME (1 << 6)
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# define OHCI_USB_OPER (2 << 6)
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# define OHCI_USB_SUSPEND (3 << 6)
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/*
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* HcCommandStatus (cmdstatus) register masks
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*/
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#define OHCI_HCR (1 << 0) /* host controller reset */
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#define OHCI_CLF (1 << 1) /* control list filled */
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#define OHCI_BLF (1 << 2) /* bulk list filled */
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#define OHCI_OCR (1 << 3) /* ownership change request */
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#define OHCI_SOC (3 << 16) /* scheduling overrun count */
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/*
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* masks used with interrupt registers:
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* HcInterruptStatus (intrstatus)
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* HcInterruptEnable (intrenable)
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* HcInterruptDisable (intrdisable)
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*/
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#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
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#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
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#define OHCI_INTR_SF (1 << 2) /* start frame */
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#define OHCI_INTR_RD (1 << 3) /* resume detect */
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#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
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#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
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#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
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#define OHCI_INTR_OC (1 << 30) /* ownership change */
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#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
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/* Virtual Root HUB */
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struct virt_root_hub {
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int devnum; /* Address of Root Hub endpoint */
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void *dev; /* was urb */
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void *int_addr;
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int send;
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int interval;
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};
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/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
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/* destination of request */
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#define RH_INTERFACE 0x01
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#define RH_ENDPOINT 0x02
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#define RH_OTHER 0x03
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#define RH_CLASS 0x20
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#define RH_VENDOR 0x40
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/* Requests: bRequest << 8 | bmRequestType */
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#define RH_GET_STATUS 0x0080
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#define RH_CLEAR_FEATURE 0x0100
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#define RH_SET_FEATURE 0x0300
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#define RH_SET_ADDRESS 0x0500
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#define RH_GET_DESCRIPTOR 0x0680
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#define RH_SET_DESCRIPTOR 0x0700
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#define RH_GET_CONFIGURATION 0x0880
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#define RH_SET_CONFIGURATION 0x0900
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#define RH_GET_STATE 0x0280
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#define RH_GET_INTERFACE 0x0A80
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#define RH_SET_INTERFACE 0x0B00
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#define RH_SYNC_FRAME 0x0C80
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/* Our Vendor Specific Request */
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#define RH_SET_EP 0x2000
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/* Hub port features */
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#define RH_PORT_CONNECTION 0x00
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#define RH_PORT_ENABLE 0x01
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#define RH_PORT_SUSPEND 0x02
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#define RH_PORT_OVER_CURRENT 0x03
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#define RH_PORT_RESET 0x04
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#define RH_PORT_POWER 0x08
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#define RH_PORT_LOW_SPEED 0x09
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#define RH_C_PORT_CONNECTION 0x10
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#define RH_C_PORT_ENABLE 0x11
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#define RH_C_PORT_SUSPEND 0x12
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#define RH_C_PORT_OVER_CURRENT 0x13
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#define RH_C_PORT_RESET 0x14
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/* Hub features */
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#define RH_C_HUB_LOCAL_POWER 0x00
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#define RH_C_HUB_OVER_CURRENT 0x01
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#define RH_DEVICE_REMOTE_WAKEUP 0x00
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#define RH_ENDPOINT_STALL 0x01
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#define RH_ACK 0x01
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#define RH_REQ_ERR -1
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#define RH_NACK 0x00
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/* OHCI ROOT HUB REGISTER MASKS */
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/* roothub.portstatus [i] bits */
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#define RH_PS_CCS 0x00000001 /* current connect status */
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#define RH_PS_PES 0x00000002 /* port enable status*/
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#define RH_PS_PSS 0x00000004 /* port suspend status */
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#define RH_PS_POCI 0x00000008 /* port over current indicator */
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#define RH_PS_PRS 0x00000010 /* port reset status */
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#define RH_PS_PPS 0x00000100 /* port power status */
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#define RH_PS_LSDA 0x00000200 /* low speed device attached */
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#define RH_PS_CSC 0x00010000 /* connect status change */
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#define RH_PS_PESC 0x00020000 /* port enable status change */
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#define RH_PS_PSSC 0x00040000 /* port suspend status change */
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#define RH_PS_OCIC 0x00080000 /* over current indicator change */
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#define RH_PS_PRSC 0x00100000 /* port reset status change */
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/* roothub.status bits */
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#define RH_HS_LPS 0x00000001 /* local power status */
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#define RH_HS_OCI 0x00000002 /* over current indicator */
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#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
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#define RH_HS_LPSC 0x00010000 /* local power status change */
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#define RH_HS_OCIC 0x00020000 /* over current indicator change */
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#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
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/* roothub.b masks */
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#define RH_B_DR 0x0000ffff /* device removable flags */
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#define RH_B_PPCM 0xffff0000 /* port power control mask */
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/* roothub.a masks */
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#define RH_A_NDP (0xff << 0) /* number of downstream ports */
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#define RH_A_PSM (1 << 8) /* power switching mode */
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#define RH_A_NPS (1 << 9) /* no power switching */
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#define RH_A_DT (1 << 10) /* device type (mbz) */
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#define RH_A_OCPM (1 << 11) /* over current protection mode */
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#define RH_A_NOCP (1 << 12) /* no over current protection */
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#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
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/* urb */
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#define N_URB_TD 48
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typedef struct
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{
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ed_t *ed;
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__u16 length; /* number of tds associated with this request */
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__u16 td_cnt; /* number of tds already serviced */
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struct usb_device *dev;
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int state;
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unsigned long pipe;
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void *transfer_buffer;
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int transfer_buffer_length;
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int interval;
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int actual_length;
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int finished;
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td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
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} urb_priv_t;
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#define URB_DEL 1
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#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
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#define NUM_TD 64 /* we need more TDs than EDs */
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#define NUM_INT_DEVS 8 /* num of ohci_dev structs for int endpoints */
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typedef struct ohci_device {
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ed_t ed[NUM_EDS] __aligned(ED_ALIGNMENT);
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td_t tds[NUM_TD] __aligned(TD_ALIGNMENT);
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int ed_cnt;
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int devnum;
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} ohci_dev_t;
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/*
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* This is the full ohci controller description
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*
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* Note how the "proper" USB information is just
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* a subset of what the full implementation needs. (Linus)
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*/
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typedef struct ohci {
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/* this allocates EDs for all possible endpoints */
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struct ohci_device ohci_dev __aligned(TD_ALIGNMENT);
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struct ohci_device int_dev[NUM_INT_DEVS] __aligned(TD_ALIGNMENT);
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struct ohci_hcca *hcca; /* hcca */
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/*dma_addr_t hcca_dma;*/
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int irq;
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int disabled; /* e.g. got a UE, we're hung */
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int sleeping;
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unsigned long flags; /* for HC bugs */
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struct ohci_regs *regs; /* OHCI controller's memory */
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int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
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ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
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ed_t *ed_bulktail; /* last endpoint of bulk list */
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ed_t *ed_controltail; /* last endpoint of control list */
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int intrstatus;
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__u32 hc_control; /* copy of the hc control reg */
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struct usb_device *dev[32];
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struct virt_root_hub rh;
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const char *slot_name;
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} ohci_t;
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#ifdef CONFIG_DM_USB
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extern struct dm_usb_ops ohci_usb_ops;
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int ohci_register(struct udevice *dev, struct ohci_regs *regs);
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int ohci_deregister(struct udevice *dev);
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#endif
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