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691d719db7
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
125 lines
3.0 KiB
C
125 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*/
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#include <altera.h>
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <init.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <ns16550.h>
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#include <watchdog.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/reset_manager_arria10.h>
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#include <asm/arch/sdram_arria10.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/nic301.h>
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#include <asm/io.h>
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#include <asm/pl310.h>
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#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
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#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
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#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q3_3 0x68
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#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q1_7 0x18
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#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
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#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
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/*
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* FPGA programming support for SoC FPGA Arria 10
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*/
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static Altera_desc altera_fpga[] = {
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{
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/* Family */
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Altera_SoCFPGA,
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/* Interface type */
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fast_passive_parallel,
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/* No limitation as additional data will be ignored */
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-1,
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/* No device function table */
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NULL,
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/* Base interface address specified in driver */
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NULL,
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/* No cookie implementation */
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0
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},
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};
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#if defined(CONFIG_SPL_BUILD)
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static struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
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(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
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/*
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+ * This function initializes security policies to be consistent across
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+ * all logic units in the Arria 10.
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+ *
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+ * The idea is to set all security policies to be normal, nonsecure
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+ * for all units.
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+ */
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void socfpga_init_security_policies(void)
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{
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/* Put OCRAM in non-secure */
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writel(0x003f0000, &noc_fw_ocram_base->region0);
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writel(0x1, &noc_fw_ocram_base->enable);
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/* Put DDR in non-secure */
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writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc);
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writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS);
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/* Enable priviledged and non-priviledged access to L4 peripherals */
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writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST);
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/* Enable secure and non-secure transactions to bridges */
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writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
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writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
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writel(0x0007FFFF,
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socfpga_get_sysmgr_addr() + SYSMGR_A10_ECC_INTMASK_SET);
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}
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void socfpga_sdram_remap_zero(void)
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{
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/* Configure the L2 controller to make SDRAM start at 0 */
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writel(0x1, &pl310->pl310_addr_filter_start);
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}
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#endif
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int arch_early_init_r(void)
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{
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/* Add device descriptor to FPGA device table */
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socfpga_fpga_add(&altera_fpga[0]);
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return 0;
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}
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/*
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* Print CPU information
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*/
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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const u32 bootinfo = readl(socfpga_get_sysmgr_addr() +
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SYSMGR_A10_BOOTINFO);
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const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
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puts("CPU: Altera SoCFPGA Arria 10\n");
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printf("BOOT: %s\n", bsel_str[bsel].name);
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return 0;
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}
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#endif
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void do_bridge_reset(int enable, unsigned int mask)
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{
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if (enable)
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socfpga_reset_deassert_bridges_handoff();
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else
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socfpga_bridges_reset();
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}
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