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114 lines
2.2 KiB
C
114 lines
2.2 KiB
C
/*
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* U-boot - cache.c
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <asm/blackfin.h>
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#include <asm/mach-common/bits/mpu.h>
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void flush_cache(unsigned long addr, unsigned long size)
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{
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void *start_addr, *end_addr;
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int istatus, dstatus;
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/* no need to flush stuff in on chip memory (L1/L2/etc...) */
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if (addr >= 0xE0000000)
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return;
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start_addr = (void *)addr;
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end_addr = (void *)(addr + size);
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istatus = icache_status();
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dstatus = dcache_status();
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if (istatus) {
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if (dstatus)
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blackfin_icache_dcache_flush_range(start_addr, end_addr);
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else
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blackfin_icache_flush_range(start_addr, end_addr);
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} else if (dstatus)
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blackfin_dcache_flush_range(start_addr, end_addr);
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}
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#ifdef CONFIG_DCACHE_WB
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static void flushinv_all_dcache(void)
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{
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u32 way, bank, subbank, set;
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u32 status, addr;
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u32 dmem_ctl = bfin_read_DMEM_CONTROL();
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for (bank = 0; bank < 2; ++bank) {
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if (!(dmem_ctl & (1 << (DMC1_P - bank))))
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continue;
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for (way = 0; way < 2; ++way)
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for (subbank = 0; subbank < 4; ++subbank)
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for (set = 0; set < 64; ++set) {
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bfin_write_DTEST_COMMAND(
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way << 26 |
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bank << 23 |
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subbank << 16 |
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set << 5
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);
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CSYNC();
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status = bfin_read_DTEST_DATA0();
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/* only worry about valid/dirty entries */
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if ((status & 0x3) != 0x3)
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continue;
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/* construct the address using the tag */
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addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
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/* flush it */
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__asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
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}
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}
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}
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#endif
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void icache_enable(void)
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{
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bfin_write_IMEM_CONTROL(IMC | ENICPLB);
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SSYNC();
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}
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void icache_disable(void)
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{
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bfin_write_IMEM_CONTROL(0);
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SSYNC();
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}
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int icache_status(void)
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{
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return bfin_read_IMEM_CONTROL() & IMC;
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}
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void dcache_enable(void)
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{
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bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
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SSYNC();
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}
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void dcache_disable(void)
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{
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#ifdef CONFIG_DCACHE_WB
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bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ENDCPLB));
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flushinv_all_dcache();
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#endif
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bfin_write_DMEM_CONTROL(0);
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SSYNC();
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}
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int dcache_status(void)
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{
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return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE;
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}
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