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1b5291dddf
u-boot/board/freescale/mpc8569mds
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Dave Liu 1b5291dddf 85xx: Fix the clock adjust of mpc8569mds board 
Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2009-06-09 22:58:05 +02:00
..
bcsr.c MPC85xx: Add MPC8569MDS board support 2009-03-30 13:33:51 -05:00
bcsr.h MPC85xx: Add MPC8569MDS board support 2009-03-30 13:33:51 -05:00
config.mk MPC85xx: Add MPC8569MDS board support 2009-03-30 13:33:51 -05:00
ddr.c 85xx: Fix the clock adjust of mpc8569mds board 2009-06-09 22:58:05 +02:00
law.c MPC85xx: Add MPC8569MDS board support 2009-03-30 13:33:51 -05:00
Makefile MPC85xx: Add MPC8569MDS board support 2009-03-30 13:33:51 -05:00
mpc8569mds.c fsl_pci: Move prototypes into fsl_pci.h and remove explicit externs 2009-04-04 10:21:30 -05:00
tlb.c MPC85xx: Add MPC8569MDS board support 2009-03-30 13:33:51 -05:00
u-boot.lds MPC85xx: Add MPC8569MDS board support 2009-03-30 13:33:51 -05:00