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b85d155199
Add the device trees for * vexpress_ca5x2_defconfig * vexpress_ca9x4_defconfig * vexpress_ca15_tc2_defconfig as available in Linux 5.1 rc5. We are using the vexpress_ca15_tc2_defconfig and vexpress_ca9x4_defconfig for Travis testing via QEMU. The UEFI base Embedded Base Boot Requirements Specification (EBBR) requires that an embedded board either provides a device tree or an ACPI table. All block devices are meant to be moved to the driver model. On ARM this requires a device tree. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
451 lines
11 KiB
Plaintext
451 lines
11 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Ltd. Versatile Express
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*
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* Motherboard Express uATX
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* V2M-P1
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*
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* HBI-0190D
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*
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* Original memory map ("Legacy memory map" in the board's
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* Technical Reference Manual)
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*
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* WARNING! The hardware described in this file is independent from the
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* RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
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* correspondence between the two configurations.
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*
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* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
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* CHANGES TO vexpress-v2m-rs1.dtsi!
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*/
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/ {
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smb@4000000 {
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motherboard {
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model = "V2M-P1";
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arm,hbi = <0x190>;
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arm,vexpress,site = <0>;
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compatible = "arm,vexpress,v2m-p1", "simple-bus";
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#address-cells = <2>; /* SMB chipselect number and offset */
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#size-cells = <1>;
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#interrupt-cells = <1>;
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ranges;
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flash@0,00000000 {
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compatible = "arm,vexpress-flash", "cfi-flash";
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reg = <0 0x00000000 0x04000000>,
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<1 0x00000000 0x04000000>;
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bank-width = <4>;
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};
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psram@2,00000000 {
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compatible = "arm,vexpress-psram", "mtd-ram";
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reg = <2 0x00000000 0x02000000>;
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bank-width = <4>;
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};
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ethernet@3,02000000 {
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compatible = "smsc,lan9118", "smsc,lan9115";
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reg = <3 0x02000000 0x10000>;
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interrupts = <15>;
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phy-mode = "mii";
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reg-io-width = <4>;
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smsc,irq-active-high;
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smsc,irq-push-pull;
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vdd33a-supply = <&v2m_fixed_3v3>;
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vddvario-supply = <&v2m_fixed_3v3>;
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};
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usb@3,03000000 {
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compatible = "nxp,usb-isp1761";
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reg = <3 0x03000000 0x20000>;
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interrupts = <16>;
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port1-otg;
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};
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iofpga@7,00000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 7 0 0x20000>;
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v2m_sysreg: sysreg@0 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x00000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x1000>;
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v2m_led_gpios: gpio@8 {
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compatible = "arm,vexpress-sysreg,sys_led";
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reg = <0x008 4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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v2m_mmc_gpios: gpio@48 {
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compatible = "arm,vexpress-sysreg,sys_mci";
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reg = <0x048 4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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v2m_flash_gpios: gpio@4c {
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compatible = "arm,vexpress-sysreg,sys_flash";
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reg = <0x04c 4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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v2m_sysctl: sysctl@1000 {
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compatible = "arm,sp810", "arm,primecell";
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reg = <0x01000 0x1000>;
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clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
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clock-names = "refclk", "timclk", "apb_pclk";
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#clock-cells = <1>;
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clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
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assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
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assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
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};
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/* PCI-E I2C bus */
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v2m_i2c_pcie: i2c@2000 {
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compatible = "arm,versatile-i2c";
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reg = <0x02000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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pcie-switch@60 {
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compatible = "idt,89hpes32h8";
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reg = <0x60>;
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};
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};
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aaci@4000 {
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compatible = "arm,pl041", "arm,primecell";
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reg = <0x04000 0x1000>;
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interrupts = <11>;
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clocks = <&smbclk>;
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clock-names = "apb_pclk";
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};
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mmci@5000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x05000 0x1000>;
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interrupts = <9>, <10>;
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cd-gpios = <&v2m_mmc_gpios 0 0>;
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wp-gpios = <&v2m_mmc_gpios 1 0>;
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max-frequency = <12000000>;
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vmmc-supply = <&v2m_fixed_3v3>;
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clocks = <&v2m_clk24mhz>, <&smbclk>;
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clock-names = "mclk", "apb_pclk";
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};
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kmi@6000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x06000 0x1000>;
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interrupts = <12>;
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clocks = <&v2m_clk24mhz>, <&smbclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@7000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x07000 0x1000>;
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interrupts = <13>;
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clocks = <&v2m_clk24mhz>, <&smbclk>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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v2m_serial0: uart@9000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x09000 0x1000>;
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interrupts = <5>;
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clocks = <&v2m_oscclk2>, <&smbclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial1: uart@a000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0a000 0x1000>;
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interrupts = <6>;
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clocks = <&v2m_oscclk2>, <&smbclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial2: uart@b000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0b000 0x1000>;
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interrupts = <7>;
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clocks = <&v2m_oscclk2>, <&smbclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial3: uart@c000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0c000 0x1000>;
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interrupts = <8>;
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clocks = <&v2m_oscclk2>, <&smbclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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wdt@f000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0f000 0x1000>;
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interrupts = <0>;
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clocks = <&v2m_refclk32khz>, <&smbclk>;
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clock-names = "wdogclk", "apb_pclk";
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};
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v2m_timer01: timer@11000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x11000 0x1000>;
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interrupts = <2>;
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clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
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clock-names = "timclken1", "timclken2", "apb_pclk";
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};
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v2m_timer23: timer@12000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x12000 0x1000>;
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interrupts = <3>;
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clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
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clock-names = "timclken1", "timclken2", "apb_pclk";
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};
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/* DVI I2C bus */
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v2m_i2c_dvi: i2c@16000 {
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compatible = "arm,versatile-i2c";
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reg = <0x16000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dvi-transmitter@39 {
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compatible = "sil,sii9022-tpi", "sil,sii9022";
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reg = <0x39>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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* Both the core tile and the motherboard routes their output
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* pads to this transmitter. The motherboard system controller
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* can select one of them as input using a mux register in
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* "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
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* the only platform with this specific set-up.
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*/
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port@0 {
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reg = <0>;
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dvi_bridge_in_ct: endpoint {
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remote-endpoint = <&clcd_pads_ct>;
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};
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};
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port@1 {
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reg = <1>;
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dvi_bridge_in_mb: endpoint {
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remote-endpoint = <&clcd_pads_mb>;
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};
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};
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};
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};
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dvi-transmitter@60 {
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compatible = "sil,sii9022-cpi", "sil,sii9022";
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reg = <0x60>;
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};
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};
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rtc@17000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x17000 0x1000>;
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interrupts = <4>;
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clocks = <&smbclk>;
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clock-names = "apb_pclk";
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};
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compact-flash@1a000 {
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compatible = "arm,vexpress-cf", "ata-generic";
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reg = <0x1a000 0x100
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0x1a100 0xf00>;
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reg-shift = <2>;
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};
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clcd@1f000 {
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compatible = "arm,pl111", "arm,primecell";
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reg = <0x1f000 0x1000>;
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interrupt-names = "combined";
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interrupts = <14>;
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clocks = <&v2m_oscclk1>, <&smbclk>;
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clock-names = "clcdclk", "apb_pclk";
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/* 800x600 16bpp @36MHz works fine */
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max-memory-bandwidth = <54000000>;
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memory-region = <&vram>;
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port {
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clcd_pads_mb: endpoint {
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remote-endpoint = <&dvi_bridge_in_mb>;
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arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
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};
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};
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};
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};
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v2m_fixed_3v3: fixed-regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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v2m_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "v2m:clk24mhz";
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};
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v2m_refclk1mhz: refclk1mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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clock-output-names = "v2m:refclk1mhz";
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};
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v2m_refclk32khz: refclk32khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "v2m:refclk32khz";
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};
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leds {
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compatible = "gpio-leds";
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user1 {
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label = "v2m:green:user1";
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gpios = <&v2m_led_gpios 0 0>;
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linux,default-trigger = "heartbeat";
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};
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user2 {
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label = "v2m:green:user2";
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gpios = <&v2m_led_gpios 1 0>;
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linux,default-trigger = "mmc0";
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};
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user3 {
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label = "v2m:green:user3";
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gpios = <&v2m_led_gpios 2 0>;
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linux,default-trigger = "cpu0";
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};
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user4 {
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label = "v2m:green:user4";
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gpios = <&v2m_led_gpios 3 0>;
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linux,default-trigger = "cpu1";
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};
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user5 {
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label = "v2m:green:user5";
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gpios = <&v2m_led_gpios 4 0>;
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linux,default-trigger = "cpu2";
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};
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user6 {
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label = "v2m:green:user6";
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gpios = <&v2m_led_gpios 5 0>;
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linux,default-trigger = "cpu3";
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};
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user7 {
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label = "v2m:green:user7";
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gpios = <&v2m_led_gpios 6 0>;
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linux,default-trigger = "cpu4";
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};
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user8 {
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label = "v2m:green:user8";
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gpios = <&v2m_led_gpios 7 0>;
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linux,default-trigger = "cpu5";
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};
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};
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mcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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oscclk0 {
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/* MCC static memory clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 0>;
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freq-range = <25000000 60000000>;
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#clock-cells = <0>;
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clock-output-names = "v2m:oscclk0";
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};
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v2m_oscclk1: oscclk1 {
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/* CLCD clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 1>;
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freq-range = <23750000 65000000>;
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#clock-cells = <0>;
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clock-output-names = "v2m:oscclk1";
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};
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v2m_oscclk2: oscclk2 {
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/* IO FPGA peripheral clock */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 2>;
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freq-range = <24000000 24000000>;
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#clock-cells = <0>;
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clock-output-names = "v2m:oscclk2";
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};
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volt-vio {
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/* Logic level voltage */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 0>;
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regulator-name = "VIO";
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regulator-always-on;
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label = "VIO";
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};
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temp-mcc {
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/* MCC internal operating temperature */
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compatible = "arm,vexpress-temp";
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arm,vexpress-sysreg,func = <4 0>;
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label = "MCC";
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};
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reset {
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compatible = "arm,vexpress-reset";
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arm,vexpress-sysreg,func = <5 0>;
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};
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muxfpga {
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compatible = "arm,vexpress-muxfpga";
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arm,vexpress-sysreg,func = <7 0>;
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};
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shutdown {
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compatible = "arm,vexpress-shutdown";
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arm,vexpress-sysreg,func = <8 0>;
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};
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reboot {
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compatible = "arm,vexpress-reboot";
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arm,vexpress-sysreg,func = <9 0>;
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};
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dvimode {
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compatible = "arm,vexpress-dvimode";
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arm,vexpress-sysreg,func = <11 0>;
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};
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};
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};
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};
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}; |