mirror of
https://github.com/u-boot/u-boot.git
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1af3c7f422
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
270 lines
7.3 KiB
C
270 lines
7.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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*
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* Configuration settings for the Armadeus Project motherboard APF27
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*
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* Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <linux/stringify.h>
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#define CONFIG_ENV_VERSION 10
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#define CONFIG_BOARD_NAME apf27
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/*
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* SoC configurations
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*/
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#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
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#define CONFIG_MACH_TYPE 1698 /* APF27 */
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/*
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* Enable the call to miscellaneous platform dependent initialization.
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*/
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/*
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* SPL
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*/
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_MAX_SIZE 2048
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/* NAND boot config */
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_HOSTNAME "apf27"
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#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
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/*
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* Memory configurations
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*/
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#define CONFIG_NR_DRAM_POPULATED 1
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#define ACFG_SDRAM_MBYTE_SYZE 64
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#define PHYS_SDRAM_1 0xA0000000
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#define PHYS_SDRAM_2 0xB0000000
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
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+ PHYS_SDRAM_1_SIZE - 0x0100000)
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/*
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* FLASH organization
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*/
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#define ACFG_MONITOR_OFFSET 0x00000000
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#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
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#define CONFIG_FIRMWARE_OFFSET 0x00200000
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#define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */
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#define CONFIG_KERNEL_OFFSET 0x00300000
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#define CONFIG_ROOTFS_OFFSET 0x00800000
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/*
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* U-Boot general configurations
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*/
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#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* Boot argument buffer size */
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/*
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* Boot Linux
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*/
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#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
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#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
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#define CONFIG_INITRD_TAG /* send initrd params */
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#define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin"
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#define ACFG_CONSOLE_DEV ttySMX0
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#define CONFIG_BOOTCOMMAND "run ubifsboot"
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#define CONFIG_SYS_AUTOLOAD "no"
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/*
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* Default load address for user programs and kernel
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*/
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#define CONFIG_LOADADDR 0xA0000000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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/*
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* Extra Environments
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
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"consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \
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"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
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"partition=nand0,6\0" \
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"u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \
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"env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \
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"firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \
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"firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \
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"kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
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"rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
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"board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
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"kernel_addr_r=A0000000\0" \
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"check_env=if test -n ${flash_env_version}; " \
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"then env default env_version; " \
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"else env set flash_env_version ${env_version}; env save; "\
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"fi; " \
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"if itest ${flash_env_version} < ${env_version}; then " \
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"echo \"*** Warning - Environment version" \
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" change suggests: run flash_reset_env; reset\"; "\
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"env default flash_reset_env; "\
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"fi; \0" \
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"check_flash=nand lock; nand unlock ${env_addr}; \0" \
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"flash_reset_env=env default -f -a; saveenv; run update_env;" \
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"echo Flash environment variables erased!\0" \
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"download_uboot=tftpboot ${loadaddr} ${board_name}" \
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"-u-boot-with-spl.bin\0" \
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"flash_uboot=nand unlock ${u-boot_addr} ;" \
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"nand erase.part u-boot;" \
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"if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
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"then nand lock; nand unlock ${env_addr};" \
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"echo Flashing of uboot succeed;" \
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"else echo Flashing of uboot failed;" \
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"fi; \0" \
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"update_uboot=run download_uboot flash_uboot\0" \
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"download_env=tftpboot ${loadaddr} ${board_name}" \
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"-u-boot-env.txt\0" \
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"flash_env=env import -t ${loadaddr}; env save; \0" \
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"update_env=run download_env flash_env\0" \
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"update_all=run update_env update_uboot\0" \
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"unlock_regs=mw 10000008 0; mw 10020008 0\0" \
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/*
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* Serial Driver
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*/
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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/*
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* NOR
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*/
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/*
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* NAND
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*/
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#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
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#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_MXC_NAND_HWECC
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#define CONFIG_SYS_NAND_LARGEPAGE
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE
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#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 11
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#define NAND_MAX_CHIPS 1
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#define CONFIG_FLASH_SHOW_PROGRESS 45
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#define CONFIG_SYS_NAND_QUIET 1
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/*
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* Partitions & Filsystems
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*/
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/*
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* Ethernet (on SOC imx FEC)
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*/
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_MXC_PHYADDR 0x1f
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/*
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* FPGA
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*/
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#define CONFIG_FPGA_COUNT 1
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#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
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#define CONFIG_SYS_FPGA_PROG_FEEDBACK
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#define CONFIG_SYS_FPGA_CHECK_CTRLC
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#define CONFIG_SYS_FPGA_CHECK_ERROR
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/*
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* Fuses - IIM
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*/
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#ifdef CONFIG_CMD_IMX_FUSE
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#define IIM_MAC_BANK 0
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#define IIM_MAC_ROW 5
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#define IIM0_SCC_KEY 11
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#define IIM1_SUID 1
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#endif
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/*
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* I2C
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*/
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#ifdef CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
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#define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_I2C_NOPROBES { }
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#ifdef CONFIG_CMD_EEPROM
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# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
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# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
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#endif /* CONFIG_CMD_EEPROM */
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#endif /* CONFIG_CMD_I2C */
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/*
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* SD/MMC
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*/
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
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#endif
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/*
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* RTC
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*/
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#ifdef CONFIG_CMD_DATE
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#define CONFIG_RTC_DS1374
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#define CONFIG_SYS_RTC_BUS_NUM 0
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#endif /* CONFIG_CMD_DATE */
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/*
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* PLL
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*
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* 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
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* |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
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*/
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#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
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#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
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/* micron 64MB */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
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#endif
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#if (ACFG_SDRAM_MBYTE_SYZE == 128)
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/* micron 128MB */
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
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#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
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#endif
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#if (ACFG_SDRAM_MBYTE_SYZE == 256)
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/* micron 256MB */
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#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
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#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
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#endif
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#endif /* __CONFIG_H */
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