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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
130 lines
3.1 KiB
C
130 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale i.MX28 GPIO control code
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#if defined(CONFIG_MX23)
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#define PINCTRL_BANKS 3
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#define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10))
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#define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10))
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#define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10))
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#define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10))
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#define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10))
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#define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10))
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#elif defined(CONFIG_MX28)
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#define PINCTRL_BANKS 5
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#define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10))
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#define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10))
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#define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10))
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#define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10))
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#define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10))
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#define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10))
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#else
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#error "Please select CONFIG_MX23 or CONFIG_MX28"
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#endif
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#define GPIO_INT_FALL_EDGE 0x0
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#define GPIO_INT_LOW_LEV 0x1
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#define GPIO_INT_RISE_EDGE 0x2
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#define GPIO_INT_HIGH_LEV 0x3
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#define GPIO_INT_LEV_MASK (1 << 0)
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#define GPIO_INT_POL_MASK (1 << 1)
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void mxs_gpio_init(void)
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{
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int i;
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for (i = 0; i < PINCTRL_BANKS; i++) {
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writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i));
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writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i));
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/* Use SCT address here to clear the IRQSTAT bits */
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writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8);
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}
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}
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int gpio_get_value(unsigned gpio)
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{
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uint32_t bank = PAD_BANK(gpio);
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uint32_t offset = PINCTRL_DIN(bank);
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struct mxs_register_32 *reg =
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(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
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return (readl(®->reg) >> PAD_PIN(gpio)) & 1;
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}
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void gpio_set_value(unsigned gpio, int value)
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{
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uint32_t bank = PAD_BANK(gpio);
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uint32_t offset = PINCTRL_DOUT(bank);
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struct mxs_register_32 *reg =
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(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
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if (value)
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writel(1 << PAD_PIN(gpio), ®->reg_set);
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else
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writel(1 << PAD_PIN(gpio), ®->reg_clr);
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}
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int gpio_direction_input(unsigned gpio)
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{
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uint32_t bank = PAD_BANK(gpio);
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uint32_t offset = PINCTRL_DOE(bank);
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struct mxs_register_32 *reg =
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(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
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writel(1 << PAD_PIN(gpio), ®->reg_clr);
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return 0;
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}
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int gpio_direction_output(unsigned gpio, int value)
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{
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uint32_t bank = PAD_BANK(gpio);
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uint32_t offset = PINCTRL_DOE(bank);
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struct mxs_register_32 *reg =
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(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
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gpio_set_value(gpio, value);
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writel(1 << PAD_PIN(gpio), ®->reg_set);
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return 0;
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}
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int gpio_request(unsigned gpio, const char *label)
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{
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if (PAD_BANK(gpio) >= PINCTRL_BANKS)
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return -1;
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return 0;
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}
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int gpio_free(unsigned gpio)
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{
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return 0;
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}
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int name_to_gpio(const char *name)
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{
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unsigned bank, pin;
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char *end;
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bank = simple_strtoul(name, &end, 10);
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if (!*end || *end != ':')
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return bank;
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pin = simple_strtoul(end + 1, NULL, 10);
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return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT);
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}
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