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c2ae7d8220
Move the SPL settings into common/spl where most of the SPL code is kept. Signed-off-by: Simon Glass <sjg@chromium.org>
22 lines
576 B
Plaintext
22 lines
576 B
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_SUNXI=y
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CONFIG_MACH_SUN6I=y
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CONFIG_DRAM_ZQ=120
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CONFIG_INITIAL_USB_SCAN_DELAY=2000
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CONFIG_USB1_VBUS_PIN="PC27"
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CONFIG_USB2_VBUS_PIN=""
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CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
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CONFIG_SPL=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FPGA is not set
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_AXP_DCDC1_VOLT=3300
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CONFIG_AXP_ALDO1_VOLT=3300
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CONFIG_AXP_DLDO1_VOLT=3300
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CONFIG_AXP_DLDO4_VOLT=3300
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_MUSB_HOST=y
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