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0e94a7113a
Since MACH_TYPE_ORIGEN is updated on mach-types, remove the MACH_TYPE_ORIGEN on config file. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Chander Kashyap <chander.kashyap@linaro.org>
170 lines
5.3 KiB
C
170 lines
5.3 KiB
C
/*
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* Copyright (C) 2011 Samsung Electronics
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*
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* Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_SAMSUNG 1 /* SAMSUNG core */
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#define CONFIG_S5P 1 /* S5P Family */
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#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
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#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* Keep L2 Cache Disabled */
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#define CONFIG_L2_OFF 1
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#define CONFIG_SYS_DCACHE_OFF 1
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define CONFIG_SYS_TEXT_BASE 0x43E00000
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/* input clock of PLL: ORIGEN has 24MHz input clock */
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#define CONFIG_SYS_CLK_FREQ 24000000
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_INITRD_TAG
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN
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/* Power Down Modes */
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#define S5P_CHECK_SLEEP 0x00000BAD
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#define S5P_CHECK_DIDLE 0xBAD00000
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#define S5P_CHECK_LPA 0xABAD0000
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
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/* select serial console configuration */
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#define CONFIG_SERIAL_MULTI 1
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#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
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#define CONFIG_BAUDRATE 115200
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#define EXYNOS4_DEFAULT_UART_OFFSET 0x020000
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/* SD/MMC configuration */
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#define CONFIG_GENERIC_MMC 1
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#define CONFIG_MMC 1
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#define CONFIG_S5P_MMC 1
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/* PWM */
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#define CONFIG_PWM 1
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* Command definition*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_FAT
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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/* MMC SPL */
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#define CONFIG_SPL
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#define COPY_BL2_FNPTR_ADDR 0x02020030
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#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_PROMPT "ORIGEN # "
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/
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#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
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#define CONFIG_SYS_HZ 1000
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* Stack sizes */
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#define CONFIG_STACKSIZE (256 << 10) /* 256KB */
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/* ORIGEN has 4 bank of DRAM */
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#define CONFIG_NR_DRAM_BANKS 4
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#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
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#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
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#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
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/* FLASH and environment organization */
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#define CONFIG_SYS_NO_FLASH 1
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#undef CONFIG_CMD_IMLS
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#define CONFIG_IDENT_STRING " for ORIGEN"
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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#define CONFIG_CLK_1000_400_200
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/* MIU (Memory Interleaving Unit) */
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#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
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#define CONFIG_ENV_IS_IN_MMC 1
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
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#define RESERVE_BLOCK_SIZE (512)
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#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
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#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE)
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
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/* U-boot copy size from boot Media to DRAM.*/
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#define COPY_BL2_SIZE 0x80000
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#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
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#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
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/* Enable devicetree support */
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#define CONFIG_OF_LIBFDT
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#endif /* __CONFIG_H */
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