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53 lines
2.0 KiB
C
53 lines
2.0 KiB
C
#ifndef _405GP_PCI_H
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#define _405GP_PCI_H
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/*----------------------------------------------------------------------------+
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| 405GP PCI core memory map defines.
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+----------------------------------------------------------------------------*/
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#define MIN_PCI_MEMADDR1 0x80000000
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#define MIN_PCI_MEMADDR2 0x00000000
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#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */
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#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */
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#define MAX_PCI_DEVICES 32
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/*----------------------------------------------------------------------------+
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| Defines for the 405GP PCI Config address and data registers followed by
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| defines for the standard PCI device configuration header.
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+----------------------------------------------------------------------------*/
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#define PCICFGADR 0xEEC00000
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#define PCICFGDATA 0xEEC00004
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#define PCIBUSNUM 0x40 /* 405GP specific parameters */
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#define PCISUBBUSNUM 0x41
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#define PCIDISCOUNT 0x42
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#define PCIBRDGOPT1 0x4A
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#define PCIBRDGOPT2 0x60
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/*----------------------------------------------------------------------------+
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| Defines for 405GP PCI Master local configuration regs.
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+----------------------------------------------------------------------------*/
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#define PMM0LA 0xEF400000
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#define PMM0MA 0xEF400004
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#define PMM0PCILA 0xEF400008
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#define PMM0PCIHA 0xEF40000C
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#define PMM1LA 0xEF400010
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#define PMM1MA 0xEF400014
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#define PMM1PCILA 0xEF400018
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#define PMM1PCIHA 0xEF40001C
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#define PMM2LA 0xEF400020
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#define PMM2MA 0xEF400024
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#define PMM2PCILA 0xEF400028
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#define PMM2PCIHA 0xEF40002C
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/*----------------------------------------------------------------------------+
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| Defines for 405GP PCI Target local configuration regs.
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+----------------------------------------------------------------------------*/
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#define PTM1MS 0xEF400030
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#define PTM1LA 0xEF400034
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#define PTM2MS 0xEF400038
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#define PTM2LA 0xEF40003C
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#define PCIDEVID_405GP 0x0
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#endif
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