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067716bac5
u-boot/include/configs/ti_armv7_keystone2.h
Tom Rini 067716bac5 ARM: Move SYS_CACHELINE_SIZE over to Kconfig 
This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.  Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: "Pali Rohár" <pali.rohar@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Alison Wang <b18965@freescale.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Saksham Jain <saksham.jain@nxp.com>
Cc: Qianyu Gong <qianyu.gong@nxp.com>
Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
Cc: tang yuantian <Yuantian.Tang@freescale.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Anand Moon <linux.amoon@gmail.com>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Carlo Caione <carlo@endlessm.com>
Cc: huang lin <hl@rock-chips.com>
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: "Andrew F. Davis" <afd@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Carlos Hernandez <ceh@ti.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Chin Liang See <clsee@altera.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
2016-08-26 17:04:46 -04:00

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/*
* Common configuration header file for all Keystone II EVM platforms
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_KS2_EVM_H
#define __CONFIG_KS2_EVM_H
#define CONFIG_SOC_KEYSTONE
/* U-Boot Build Configuration */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_ARCH_TIMER
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x0c000000
#endif
#define CONFIG_SPL_TARGET "u-boot-spi.gph"
#define CONFIG_SYS_DCACHE_OFF
/* Memory Configuration */
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \
GENERATED_GBL_DATA_SIZE)
#ifdef CONFIG_SYS_MALLOC_F_LEN
#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN
#else
#define SPL_MALLOC_F_SIZE 0
#endif
/* SPL SPI Loader Configuration */
#define CONFIG_SPL_PAD_TO 65536
#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8)
#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \
CONFIG_SPL_MAX_SIZE)
#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024)
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024)
#define CONFIG_SPL_STACK_SIZE (8 * 1024)
#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \
CONFIG_SYS_SPL_MALLOC_SIZE + \
SPL_MALLOC_F_SIZE + \
CONFIG_SPL_STACK_SIZE - 4)
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
/* UART Configuration */
#define CONFIG_SYS_NS16550_MEM32
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#endif
#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
#define CONFIG_CONS_INDEX 1
#ifndef CONFIG_SOC_K2G
#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
#else
#define CONFIG_SYS_NS16550_CLK clk_get_rate(uart_pll_clk) / 2
#endif
/* SPI Configuration */
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_SYS_SPI0
#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE
#define CONFIG_SYS_SPI0_NUM_CS 4
#define CONFIG_SYS_SPI1
#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE
#define CONFIG_SYS_SPI1_NUM_CS 4
#define CONFIG_SYS_SPI2
#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE
#define CONFIG_SYS_SPI2_NUM_CS 4
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_SPI
#undef CONFIG_DM_SPI_FLASH
#endif
/* Network Configuration */
#define CONFIG_PHYLIB
#define CONFIG_PHY_MARVELL
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 32
#define CONFIG_SYS_SGMII_REFCLK_MHZ 312
#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
#define CONFIG_SYS_SGMII_RATESCALE 2
/* Keyston Navigator Configuration */
#define CONFIG_TI_KSNAV
#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS
#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE
#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE
#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE
#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE
#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE
#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE
#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE
#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE
#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE
#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE
#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE
#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM
#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM
/* NETCP pktdma */
#define CONFIG_KSNAV_PKTDMA_NETCP
#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM
#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM
#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM
#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE
#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE
#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE
/* Keystone net */
#define CONFIG_DRIVER_TI_KEYSTONE_NET
#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE
#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
/* SerDes */
#define CONFIG_TI_KEYSTONE_SERDES
#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
/* I2C Configuration */
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
#define I2C_BUS_MAX 3
/* EEPROM definitions */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
#define CONFIG_ENV_EEPROM_IS_ON_I2C
/* NAND Configuration */
#define CONFIG_NAND_DAVINCI
#define CONFIG_KEYSTONE_RBL_NAND
#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET
#define CONFIG_SYS_NAND_MASK_CLE 0x4000
#define CONFIG_SYS_NAND_MASK_ALE 0x2000
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x100000
#define CONFIG_MTD_PARTITIONS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
"1024k(bootloader)ro,512k(params)ro," \
"-(ubifs)"
/* USB Configuration */
#define CONFIG_USB_XHCI_KEYSTONE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
#define CONFIG_EFI_PARTITION
#define CONFIG_FS_FAT
#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE
#define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE
/* U-Boot command configuration */
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_EEPROM
/* U-Boot general configuration */
#define CONFIG_MISC_INIT_R
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
#define CONFIG_TIMESTAMP
/* EDMA3 */
#define CONFIG_TI_EDMA3
#define DEFAULT_FW_INITRAMFS_BOOT_ENV \
"name_fw_rd=k2-fw-initrd.cpio.gz\0" \
"set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0" \
"init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; " \
"run set_rd_spec\0" \
"init_fw_rd_ramfs=setenv rd_spec -\0" \
"init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; " \
"run set_rd_spec\0" \
#define DEFAULT_PMMC_BOOT_ENV \
"set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \
"dev_pmmc=0\0" \
"get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0" \
"get_pmmc_ramfs=run get_pmmc_net\0" \
"get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} " \
"${bootdir}/${name_pmmc}\0" \
"get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}\0" \
"run_pmmc=rproc init; rproc list; " \
"rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; " \
"rproc start ${dev_pmmc}\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
"bootdir=/boot\0" \
"tftp_root=/\0" \
"nfs_root=/export\0" \
"mem_lpae=1\0" \
"addr_ubi=0x82000000\0" \
"addr_secdb_key=0xc000000\0" \
"name_kern=zImage\0" \
"run_mon=mon_install ${addr_mon}\0" \
"run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0" \
"init_net=run args_all args_net\0" \
"init_nfs=setenv autoload no; dhcp; run args_all args_net\0" \
"init_ubi=run args_all args_ubi; " \
"ubi part ubifs; ubifsmount ubi:rootfs;\0" \
"get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \
"get_fdt_nfs=nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt}\0" \
"get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0" \
"get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \
"get_kern_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_kern}\0" \
"get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0" \
"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
"get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0" \
"get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0" \
"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \
"get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \
"burn_uboot_spi=sf probe; sf erase 0 0x80000; " \
"sf write ${loadaddr} 0 ${filesize}\0" \
"burn_uboot_nand=nand erase 0 0x100000; " \
"nand write ${loadaddr} 0 ${filesize}\0" \
"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
"args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
"${nfs_options} ip=dhcp\0" \
"nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \
"get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \
"get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \
"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
"get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \
"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
"get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0" \
"burn_ubi=nand erase.part ubifs; " \
"nand write ${addr_ubi} ubifs ${filesize}\0" \
"init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \
"args_ramfs=setenv bootargs ${bootargs} " \
"rdinit=/sbin/init rw root=/dev/ram0 " \
"initrd=0x808080000,80M\0" \
"no_post=1\0" \
"mtdparts=mtdparts=davinci_nand.0:" \
"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
#ifndef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND \
"run init_${boot} init_fw_rd_${boot} get_fdt_${boot} " \
"get_mon_${boot} get_kern_${boot} run_mon run_kern"
#endif
#define CONFIG_BOOTARGS \
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
/* We wont be loading up OS from SPL for now.. */
#undef CONFIG_SPL_OS_BOOT
/* We do not have MMC support.. yet.. */
#undef CONFIG_SPL_LIBDISK_SUPPORT
#undef CONFIG_SPL_MMC_SUPPORT
#undef CONFIG_SPL_FAT_SUPPORT
#undef CONFIG_SPL_EXT_SUPPORT
#undef CONFIG_MMC
#undef CONFIG_GENERIC_MMC
/* And no support for GPIO, yet.. */
#undef CONFIG_SPL_GPIO_SUPPORT
/* we may include files below only after all above definitions */
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#ifndef CONFIG_SOC_K2G
#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
#else
#define CONFIG_SYS_HZ_CLOCK external_clk[sys_clk]
#endif
#endif /* __CONFIG_KS2_EVM_H */
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