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222 lines
6.8 KiB
C
222 lines
6.8 KiB
C
/*
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* (C) Copyright 2007 STMicroelectronics, <www.st.com>
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* (C) Copyright 2009 Alessandro Rubini <rubini@unipv.it>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <nand.h>
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#include <asm/io.h>
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static inline int parity(int b) /* b is really a byte; returns 0 or ~0 */
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{
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__asm__ __volatile__(
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"eor %0, %0, %0, lsr #4\n\t"
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"eor %0, %0, %0, lsr #2\n\t"
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"eor %0, %0, %0, lsr #1\n\t"
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"ands %0, %0, #1\n\t"
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"subne %0, %0, #2\t"
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: "=r" (b) : "0" (b));
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return b;
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}
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/*
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* This is the ECC routine used in hardware, according to the manual.
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* HW claims to make the calculation but not the correction; so we must
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* recalculate the bytes for a comparison.
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*/
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static int ecc512(const unsigned char *data, unsigned char *ecc)
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{
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int gpar = 0;
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int i, val, par;
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int pbits = 0; /* P8, P16, ... P2048 */
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int pprime = 0; /* P8', P16', ... P2048' */
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int lowbits; /* P1, P2, P4 and primes */
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for (i = 0; i < 512; i++) {
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par = parity((val = data[i]));
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gpar ^= val;
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pbits ^= (i & par);
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}
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/*
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* Ok, now gpar is global parity (xor of all bytes)
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* pbits are all the parity bits (non-prime ones)
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*/
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par = parity(gpar);
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pprime = pbits ^ par;
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/* Put low bits in the right position for ecc[2] (bits 7..2) */
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lowbits = 0
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| (parity(gpar & 0xf0) & 0x80) /* P4 */
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| (parity(gpar & 0x0f) & 0x40) /* P4' */
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| (parity(gpar & 0xcc) & 0x20) /* P2 */
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| (parity(gpar & 0x33) & 0x10) /* P2' */
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| (parity(gpar & 0xaa) & 0x08) /* P1 */
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| (parity(gpar & 0x55) & 0x04); /* P1' */
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ecc[2] = ~(lowbits | ((pbits & 0x100) >> 7) | ((pprime & 0x100) >> 8));
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/* now intermix bits for ecc[1] (P1024..P128') and ecc[0] (P64..P8') */
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ecc[1] = ~( (pbits & 0x80) >> 0 | ((pprime & 0x80) >> 1)
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| ((pbits & 0x40) >> 1) | ((pprime & 0x40) >> 2)
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| ((pbits & 0x20) >> 2) | ((pprime & 0x20) >> 3)
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| ((pbits & 0x10) >> 3) | ((pprime & 0x10) >> 4));
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ecc[0] = ~( (pbits & 0x8) << 4 | ((pprime & 0x8) << 3)
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| ((pbits & 0x4) << 3) | ((pprime & 0x4) << 2)
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| ((pbits & 0x2) << 2) | ((pprime & 0x2) << 1)
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| ((pbits & 0x1) << 1) | ((pprime & 0x1) << 0));
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return 0;
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}
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/* This is the method in the chip->ecc field */
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static int nomadik_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc_code)
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{
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return ecc512(dat, ecc_code);
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}
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static int nomadik_ecc_correct(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *r_ecc, uint8_t *c_ecc)
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{
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struct nand_chip *chip = mtd->priv;
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uint32_t r, c, d, diff; /*read, calculated, xor of them */
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if (!memcmp(r_ecc, c_ecc, chip->ecc.bytes))
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return 0;
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/* Reorder the bytes into ascending-order 24 bits -- see manual */
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r = r_ecc[2] << 22 | r_ecc[1] << 14 | r_ecc[0] << 6 | r_ecc[2] >> 2;
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c = c_ecc[2] << 22 | c_ecc[1] << 14 | c_ecc[0] << 6 | c_ecc[2] >> 2;
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diff = (r ^ c) & ((1<<24)-1); /* use 24 bits only */
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/* If 12 bits are different, one per pair, it's correctable */
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if (((diff | (diff>>1)) & 0x555555) == 0x555555) {
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int bit = ((diff & 2) >> 1)
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| ((diff & 0x8) >> 2) | ((diff & 0x20) >> 3);
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int byte;
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d = diff >> 6; /* remove bit-order info */
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byte = ((d & 2) >> 1)
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| ((d & 0x8) >> 2) | ((d & 0x20) >> 3)
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| ((d & 0x80) >> 4) | ((d & 0x200) >> 5)
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| ((d & 0x800) >> 6) | ((d & 0x2000) >> 7)
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| ((d & 0x8000) >> 8) | ((d & 0x20000) >> 9);
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/* correct the single bit */
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dat[byte] ^= 1<<bit;
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return 0;
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}
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/* If 1 bit only differs, it's one bit error in ECC, ignore */
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if ((diff ^ (1 << (ffs(diff) - 1))) == 0)
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return 0;
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/* Otherwise, uncorrectable */
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return -1;
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}
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static void nomadik_ecc_hwctl(struct mtd_info *mtd, int mode)
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{ /* mandatory in the structure but not used here */ }
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/* This is the layout used by older installations, we keep compatible */
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struct nand_ecclayout nomadik_ecc_layout = {
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.eccbytes = 3 * 4,
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.eccpos = { /* each subpage has 16 bytes: pos 2,3,4 hosts ECC */
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0x02, 0x03, 0x04,
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0x12, 0x13, 0x14,
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0x22, 0x23, 0x24,
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0x32, 0x33, 0x34},
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.oobfree = { {0x08, 0x08}, {0x18, 0x08}, {0x28, 0x08}, {0x38, 0x08} },
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};
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#define MASK_ALE (1 << 24) /* our ALE is AD21 */
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#define MASK_CLE (1 << 23) /* our CLE is AD22 */
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/* This is copied from the AT91SAM9 devices (Stelian Pop, Lead Tech Design) */
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static void nomadik_nand_hwcontrol(struct mtd_info *mtd,
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int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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u32 pcr0 = readl(REG_FSMC_PCR0);
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if (ctrl & NAND_CTRL_CHANGE) {
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ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
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IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
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if (ctrl & NAND_CLE)
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IO_ADDR_W |= MASK_CLE;
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if (ctrl & NAND_ALE)
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IO_ADDR_W |= MASK_ALE;
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if (ctrl & NAND_NCE)
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writel(pcr0 | 0x4, REG_FSMC_PCR0);
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else
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writel(pcr0 & ~0x4, REG_FSMC_PCR0);
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this->IO_ADDR_W = (void *) IO_ADDR_W;
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this->IO_ADDR_R = (void *) IO_ADDR_W;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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/* Returns 1 when ready; upper layers timeout at 20ms with timer routines */
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static int nomadik_nand_ready(struct mtd_info *mtd)
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{
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return 1; /* The ready bit is handled in hardware */
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}
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/* Copy a buffer 32bits at a time: faster than defualt method which is 8bit */
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static void nomadik_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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int i;
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struct nand_chip *chip = mtd->priv;
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u32 *p = (u32 *) buf;
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len >>= 2;
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writel(0, REG_FSMC_ECCR0);
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for (i = 0; i < len; i++)
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p[i] = readl(chip->IO_ADDR_R);
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}
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int board_nand_init(struct nand_chip *chip)
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{
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/* Set up the FSMC_PCR0 for nand access*/
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writel(0x0000004a, REG_FSMC_PCR0);
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/* Set up FSMC_PMEM0, FSMC_PATT0 with timing data for access */
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writel(0x00020401, REG_FSMC_PMEM0);
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writel(0x00020404, REG_FSMC_PATT0);
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chip->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
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chip->cmd_ctrl = nomadik_nand_hwcontrol;
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chip->dev_ready = nomadik_nand_ready;
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/* The chip allows 32bit reads, so avoid the default 8bit copy */
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chip->read_buf = nomadik_nand_read_buf;
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/* ECC: follow the hardware-defined rulse, but do it in sw */
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.bytes = 3;
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chip->ecc.size = 512;
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chip->ecc.layout = &nomadik_ecc_layout;
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chip->ecc.calculate = nomadik_ecc_calculate;
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chip->ecc.hwctl = nomadik_ecc_hwctl;
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chip->ecc.correct = nomadik_ecc_correct;
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return 0;
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}
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