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2931342874
Now that xHCD does not use CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS, remove it in all boards' config files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
157 lines
4.2 KiB
C
157 lines
4.2 KiB
C
/*
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* cm_t43.h
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*
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* Copyright (C) 2015 Compulab, Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_CM_T43_H
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#define __CONFIG_CM_T43_H
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#define CONFIG_CM_T43
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
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#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
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#include <asm/arch/omap.h>
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/* Serial support */
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_CLK 48000000
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#define CONFIG_SYS_NS16550_COM1 0x44e09000
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#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#endif
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/* NAND support */
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#define CONFIG_NAND
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#define CONFIG_NAND_OMAP_ELM
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 14
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
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10, 11, 12, 13, 14, 15, 16, 17, \
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18, 19, 20, 21, 22, 23, 24, 25, \
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26, 27, 28, 29, 30, 31, 32, 33, \
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34, 35, 36, 37, 38, 39, 40, 41, \
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42, 43, 44, 45, 46, 47, 48, 49, \
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50, 51, 52, 53, 54, 55, 56, 57, }
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/* CPSW Ethernet support */
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#define CONFIG_DRIVER_TI_CPSW
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#define CONFIG_MII
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#define CONFIG_BOOTP_DEFAULT
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_NET_MULTI
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHY_ATHEROS
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#define CONFIG_PHYLIB
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#define CONFIG_SYS_RX_ETH_BUFFER 64
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/* USB support */
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#define CONFIG_USB_XHCI_OMAP
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#define CONFIG_OMAP_USB_PHY
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#define CONFIG_AM437X_USB2PHY2_HOST
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/* SPI Flash support */
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#define CONFIG_TI_SPI_MMAP
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#define CONFIG_SF_DEFAULT_SPEED 48000000
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#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
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/* Power */
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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#define CONFIG_POWER_TPS65218
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/* Enabling L2 Cache */
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#define CONFIG_SYS_L2_PL310
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#define CONFIG_SYS_PL310_BASE 0x48242000
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/*
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* Since SPL did pll and ddr initialization for us,
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* we don't need to do it twice.
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*/
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#if !defined(CONFIG_SPL_BUILD)
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif
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#define CONFIG_HSMMC2_8BIT
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#include <configs/ti_armv7_omap.h>
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#undef CONFIG_SYS_MONITOR_LEN
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#define CONFIG_ENV_SIZE (16 * 1024)
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#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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#define V_OSCK 24000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK)
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_ENV_OFFSET (768 * 1024)
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#define CONFIG_ENV_SPI_MAX_HZ 48000000
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#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x80200000\0" \
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"fdtaddr=0x81200000\0" \
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"bootm_size=0x8000000\0" \
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"autoload=no\0" \
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"console=ttyO0,115200n8\0" \
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"fdtfile=am437x-sb-som-t43.dtb\0" \
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"kernel=zImage-cm-t43\0" \
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"bootscr=bootscr.img\0" \
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"emmcroot=/dev/mmcblk0p2 rw\0" \
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"emmcrootfstype=ext4 rootwait\0" \
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"emmcargs=setenv bootargs console=${console} " \
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"root=${emmcroot} " \
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"rootfstype=${emmcrootfstype}\0" \
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"loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source ${loadaddr}\0" \
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"emmcboot=echo Booting from emmc ... && " \
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"run emmcargs && " \
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"load mmc 1 ${loadaddr} ${kernel} && " \
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"load mmc 1 ${fdtaddr} ${fdtfile} && " \
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"bootz ${loadaddr} - ${fdtaddr}\0"
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#define CONFIG_BOOTCOMMAND \
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"mmc dev 0; " \
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"if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"fi; " \
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"fi; " \
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"mmc dev 1; " \
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"if mmc rescan; then " \
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"run emmcboot; " \
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"fi;"
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#define CONFIG_CONS_INDEX 1
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/* SPL defines. */
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#define CONFIG_SPL_TEXT_BASE 0x40300350
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#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
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#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SPL_SPI_LOAD
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/* EEPROM */
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#define CONFIG_ENV_EEPROM_IS_ON_I2C
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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#define CONFIG_SYS_EEPROM_SIZE 256
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#endif /* __CONFIG_CM_T43_H */
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