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371dc068bb
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org>
275 lines
6.8 KiB
C
275 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Xilinx Zynq MPSoC Mailbox driver
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*
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* Copyright (C) 2018-2019 Xilinx, Inc.
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*/
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#include <log.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <dm.h>
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#include <mailbox-uclass.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <dm/of_access.h>
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#include <linux/arm-smccc.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <wait_bit.h>
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#include <zynqmp_firmware.h>
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/* IPI bitmasks, register base */
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/* TODO: move reg base to DT */
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#define IPI_BIT_MASK_PMU0 0x10000
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#define IPI_INT_REG_BASE_APU 0xFF300000
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/* IPI agent ID any */
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#define IPI_ID_ANY 0xFFUL
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/* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */
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#define USE_SMC 0
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/* Default IPI SMC function IDs */
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#define SMC_IPI_MAILBOX_OPEN 0x82001000U
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#define SMC_IPI_MAILBOX_RELEASE 0x82001001U
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#define SMC_IPI_MAILBOX_STATUS_ENQUIRY 0x82001002U
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#define SMC_IPI_MAILBOX_NOTIFY 0x82001003U
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#define SMC_IPI_MAILBOX_ACK 0x82001004U
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#define SMC_IPI_MAILBOX_ENABLE_IRQ 0x82001005U
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#define SMC_IPI_MAILBOX_DISABLE_IRQ 0x82001006U
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/* IPI SMC Macros */
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/*
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* Flag to indicate if notification interrupt
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* to be disabled.
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*/
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#define IPI_SMC_ENQUIRY_DIRQ_MASK BIT(0)
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/*
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* Flag to indicate if notification interrupt
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* to be enabled.
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*/
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#define IPI_SMC_ACK_EIRQ_MASK BIT(0)
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/* IPI mailbox status */
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#define IPI_MB_STATUS_IDLE 0
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#define IPI_MB_STATUS_SEND_PENDING 1
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#define IPI_MB_STATUS_RECV_PENDING 2
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#define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
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#define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
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struct ipi_int_regs {
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u32 trig; /* 0x0 */
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u32 obs; /* 0x4 */
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u32 dummy0;
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u32 dummy1;
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u32 isr; /* 0x10 */
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u32 imr; /* 0x14 */
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u32 ier; /* 0x18 */
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u32 idr; /* 0x1C */
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};
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#define ipi_int_apu ((struct ipi_int_regs *)IPI_INT_REG_BASE_APU)
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struct zynqmp_ipi {
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void __iomem *local_req_regs;
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void __iomem *local_res_regs;
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void __iomem *remote_req_regs;
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void __iomem *remote_res_regs;
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u32 remote_id;
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u32 local_id;
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bool el3_supported;
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};
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static int zynqmp_ipi_fw_call(struct zynqmp_ipi *ipi_mbox,
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unsigned long a0, unsigned long a3)
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{
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struct arm_smccc_res res = {0};
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unsigned long a1, a2;
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a1 = ipi_mbox->local_id;
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a2 = ipi_mbox->remote_id;
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arm_smccc_smc(a0, a1, a2, a3, 0, 0, 0, 0, &res);
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return (int)res.a0;
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}
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static int zynqmp_ipi_send(struct mbox_chan *chan, const void *data)
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{
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const struct zynqmp_ipi_msg *msg = (struct zynqmp_ipi_msg *)data;
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struct zynqmp_ipi *zynqmp = dev_get_priv(chan->dev);
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u32 ret;
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u32 *mbx = (u32 *)zynqmp->local_req_regs;
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for (size_t i = 0; i < msg->len; i++)
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writel(msg->buf[i], &mbx[i]);
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/* Use SMC calls for Exception Level less than 3 where TF-A is available */
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if (!IS_ENABLED(CONFIG_XPL_BUILD) && current_el() < 3) {
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ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_NOTIFY, 0);
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debug("%s, send %ld bytes\n", __func__, msg->len);
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return ret;
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}
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/* Return if EL3 is not supported */
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if (!zynqmp->el3_supported) {
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dev_err(chan->dev, "mailbox in EL3 only supported for zynqmp");
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return -EOPNOTSUPP;
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}
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/* Write trigger interrupt */
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writel(IPI_BIT_MASK_PMU0, &ipi_int_apu->trig);
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/* Wait until observation bit is cleared */
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ret = wait_for_bit_le32(&ipi_int_apu->obs, IPI_BIT_MASK_PMU0, false,
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1000, false);
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debug("%s, send %ld bytes\n", __func__, msg->len);
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return ret;
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};
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static int zynqmp_ipi_recv(struct mbox_chan *chan, void *data)
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{
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struct zynqmp_ipi_msg *msg = (struct zynqmp_ipi_msg *)data;
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struct zynqmp_ipi *zynqmp = dev_get_priv(chan->dev);
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u32 *mbx = (u32 *)zynqmp->local_res_regs;
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int ret = 0;
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/*
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* PMU Firmware does not trigger IPI interrupt for API call responses so
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* there is no need to check ISR flags for EL3.
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*/
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for (size_t i = 0; i < msg->len; i++)
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msg->buf[i] = readl(&mbx[i]);
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/* Ack to remote if EL is not 3 */
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if (!IS_ENABLED(CONFIG_XPL_BUILD) && current_el() < 3) {
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ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_ACK,
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IPI_SMC_ACK_EIRQ_MASK);
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}
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debug("%s, recv %ld bytes\n", __func__, msg->len);
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return ret;
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};
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static int zynqmp_ipi_dest_probe(struct udevice *dev)
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{
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struct zynqmp_ipi *zynqmp = dev_get_priv(dev);
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struct resource res;
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ofnode node;
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int ret;
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debug("%s(dev=%p)\n", __func__, dev);
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node = dev_ofnode(dev);
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if (IS_ENABLED(CONFIG_XPL_BUILD) || of_machine_is_compatible("xlnx,zynqmp"))
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zynqmp->el3_supported = true;
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ret = dev_read_u32(dev->parent, "xlnx,ipi-id", &zynqmp->local_id);
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if (ret) {
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dev_err(dev, "can't get local ipi id\n");
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return ret;
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}
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ret = ofnode_read_u32(node, "xlnx,ipi-id", &zynqmp->remote_id);
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if (ret) {
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dev_err(dev, "can't get remote ipi id\n");
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return ret;
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}
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if (ofnode_read_resource_byname(node, "local_request_region", &res)) {
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dev_err(dev, "No reg property for local_request_region\n");
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return -EINVAL;
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};
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zynqmp->local_req_regs = devm_ioremap(dev, res.start,
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(res.start - res.end));
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if (!zynqmp->local_req_regs)
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return -EINVAL;
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if (ofnode_read_resource_byname(node, "local_response_region", &res)) {
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dev_err(dev, "No reg property for local_response_region\n");
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return -EINVAL;
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};
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zynqmp->local_res_regs = devm_ioremap(dev, res.start,
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(res.start - res.end));
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if (!zynqmp->local_res_regs)
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return -EINVAL;
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if (ofnode_read_resource_byname(node, "remote_request_region", &res)) {
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dev_err(dev, "No reg property for remote_request_region\n");
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return -EINVAL;
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};
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zynqmp->remote_req_regs = devm_ioremap(dev, res.start,
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(res.start - res.end));
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if (!zynqmp->remote_req_regs)
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return -EINVAL;
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if (ofnode_read_resource_byname(node, "remote_response_region", &res)) {
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dev_err(dev, "No reg property for remote_response_region\n");
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return -EINVAL;
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};
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zynqmp->remote_res_regs = devm_ioremap(dev, res.start,
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(res.start - res.end));
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if (!zynqmp->remote_res_regs)
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return -EINVAL;
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return 0;
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};
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static int zynqmp_ipi_probe(struct udevice *dev)
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{
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struct udevice *cdev;
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ofnode cnode;
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int ret;
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debug("%s(dev=%p)\n", __func__, dev);
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dev_for_each_subnode(cnode, dev) {
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ret = device_bind_driver_to_node(dev, "zynqmp_ipi_dest",
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ofnode_get_name(cnode),
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cnode, &cdev);
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if (ret)
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return ret;
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}
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return 0;
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};
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struct mbox_ops zynqmp_ipi_dest_mbox_ops = {
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.send = zynqmp_ipi_send,
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.recv = zynqmp_ipi_recv,
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};
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static const struct udevice_id zynqmp_ipi_dest_ids[] = {
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{ .compatible = "xlnx,zynqmp-ipi-dest-mailbox" },
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{ }
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};
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U_BOOT_DRIVER(zynqmp_ipi_dest) = {
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.name = "zynqmp_ipi_dest",
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.id = UCLASS_MAILBOX,
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.of_match = zynqmp_ipi_dest_ids,
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.probe = zynqmp_ipi_dest_probe,
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.priv_auto = sizeof(struct zynqmp_ipi),
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.ops = &zynqmp_ipi_dest_mbox_ops,
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};
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static const struct udevice_id zynqmp_ipi_ids[] = {
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{ .compatible = "xlnx,zynqmp-ipi-mailbox" },
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{ }
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};
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U_BOOT_DRIVER(zynqmp_ipi) = {
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.name = "zynqmp_ipi",
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.id = UCLASS_NOP,
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.of_match = zynqmp_ipi_ids,
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.probe = zynqmp_ipi_probe,
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.flags = DM_FLAG_PROBE_AFTER_BIND,
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};
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