Commit Graph

13656 Commits

Author SHA1 Message Date
Timur Tabi
fbb9ecf749 powerpc/mp: add support for discontiguous cores
Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more.  We define
CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions
to process the mask and enumerate over the set of valid cores.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Kumar Gala
86df5142a1 powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
We shouldn't be setting execute permissions on TLB entries that will not
actually have any code run from them.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Kumar Gala
10aeabd186 fdt: Add new fdt_create_phandle helper
Add a helper function that will return a phandle value for the given
node.  If the node doesn't have a phandle already one will be created.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
2011-09-29 19:01:05 -05:00
Kumar Gala
f117c0f073 fdt: Rename fdt_create_phandle to fdt_set_phandle
The old fdt_create_phandle didn't actually create a phandle it just
set one.  We'll introduce a new helper that actually does creation.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
2011-09-29 19:01:05 -05:00
Kumar Gala
e2d0f255cf powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
Add ifdef protection around fman specific code related to device tree
clock setup.  If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't
be executing this code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Poonam Aggrwal
bc6bbd6be8 fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
Issue: Address masking doesn't work properly.
When sum of the base address, defined by BA, and memory bank size,
defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask
CSPRn[BA] bits.

Impact:
This will impact booting when we are reprogramming CSPR0(BA) and
AMASK0(AMASK) while executing from NOR Flash.

Workaround:
Re-programming of CSPR(BA) and AMASK is done while not executing from NOR
Flash. The code which programs the BA and AMASK is executed from L2-SRAM.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Poonam Aggrwal
fb855f43a1 powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
Issue:
Peripheral connected to IFC_CS3 may hamper booting from IFC.

Impact:
Boot from IFC may not be successful if IFC_CS3 is used.

Workaround:
If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR.
Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Poonam Aggrwal
42aee64bd9 fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
Issue:
The NOR-FCM does not support access to unaligned addresses for 16 bit port size

Impact:
When 16 bit port size is used, accesses not aligned to 16 bit address boundary
will result in incorrect data

Workaround:
The workaround is to switch to GPCM mode for NOR Flash access.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Poonam Aggrwal
e8e6197ab2 powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
For an IFC Erratum (A-003399) we will need to access IFC registers in
cpu_init_early_f() so expand the TLB covering CCSR to 1M.

Since we need a TLB to cover 1M we move to using TLB1 array for all the
early mappings so we can cover various sizes beyond 4k.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Dipen Dudhat
d793e5a840 powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB
And various defines to enable NAND support and NAND spl code for the
P1010RDB platform.

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Dipen Dudhat
52f90dad60 nand: Freescale Integrated Flash Controller NAND support
Add NAND support (including spl) on IFC, such as is found on the p1010.

Note that using hardware ECC on IFC with small-page NAND (which is what
comes on the p1010rdb reference board) means there will be insufficient
OOB space for JFFS2, since IFC does not support 1-bit ECC.  UBI should
work, as it does not use OOB for anything but ECC.

When hardware ECC is not enabled in CSOR, software ECC is now used.

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
[scottwood@freescale.com: ECC rework and misc fixes]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-09-29 19:01:04 -05:00
Poonam Aggrwal
49249e137d powerpc/85xx: Add basic support for P1010RDB
Boot methods supported: NOR Flash, SPI Flash and SDCARD
This patch adds the following basic interfaces:
DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash.

P1010RDB Overview
-----------------
1Gbyte DDR3 (on board DDR)
Local Bus (IFC):
	32Mbyte 16bit NOR flash
	32Mbyte SLC NAND Flash
	64KB CPLD device(GPCM interface)
SPI Flash:
	128 Mbit SPI Flash memory
SD/MMC:
	connector to interface with the SD memory card
SATA:
	1 internal SATA connect to 2.5. 160G SATA2 HDD
	1 eSATA connector to rear panel
USB 2.0:
	x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface.
	x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet
eTSEC:
	eTSEC1: Connected to RGMII PHY VSC8641XKO
	eTSEC2: Connected to SGMII PHY VSC8221
	eTSEC3: Connected to SGMII PHY VSC8221
eCAN:
	Two DB-9 female connectors for Field bus interface
UART:
	supports two UARTs up to 115200 bps for console
TDM:
	2 FXS ports connected via an external SLIC to the TDM interface.
SLIC:
	SPI SLIC
I2C:
	Serial EEprom
	Real time clock
	256 Kbit M24256 I2C EEPROM
PCIe:
	PCIe and mPCIe connectors.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Li Yang
14aa71e660 powerpc/85xx: Add support for new P102x/P2020 RDB style boards
The following boards share a common design but with minor variations
between them:

P1020MSBG-PC
P1020RDB-PC
P1020UTM-PC
P1021RDB-PC
P1024RDB
P1025RDB
P2020RDB-PC

The P1020RDB-PC shares its roots in the existing P1020RDB board design,
however uses DDR3 instead of DDR2.
P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK.

Key features on these boards include:
* DDR3
* NOR flash
* NAND flash (on RDB's only)
* SPI flash (on RDB's only)
* SDHC/MMC card slot
* VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
* PCIE slot and mini-PCIE slots

As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
is used to store SPD data. In case of absent or corrupted SPD, falling back
to timing data embedded in the source code will be used. Raw timing data is
extracted from DDR chip datasheet. Different speeds of DDR are supported
with this approach. ODT option is forced to fit this set of boards, again
because they don't have regular DIMMs.

CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet
specification for writing timing.

VSC firmware Address is defined by default in config file for eTSEC1.

SD width is based off DIP switch. DIP switch is detected on the
board by reading i2c bus and setting the appropriate mux values.

Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC
have pins multiplexing. QE function needs to be disabled to access Nor Flash
and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below

'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Zhao Chenhui <b26998@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Tang Yuantian <b29983@freescale.com>
Signed-off-by: ramneek.mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>
2011-09-29 19:01:04 -05:00
Timur Tabi
6ca88b0958 powerpc/85xx: relocate CCSR before creating the initial RAM area
Before main memory (DDR) is initialized, the on-chip L1 cache is used as a
memory area for the stack and the global data (gd_t) structure.  This is
called the initial RAM area, or initram.  The L1 cache is locked and the TLBs
point to a non-existent address (so that there's no chance it will overlap
main memory or any device).  The L1 cache is also configured not to write
out to memory or the L2 cache, so everything stays in the L1 cache.

One of the things we might do while running out of initram is relocate CCSR.
On reset, CCSR is typically located at some high 32-bit address, like
0xfe000000, and this may not be the best place for CCSR.  For example, on
36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit
memory space.

On some future Freescale SOCs, the L1 cache will be forced to write to the
backing store, so we can no longer have the TLBs point to non-existent address.
Instead, we will point the TLBs to an unused area in CCSR.  In order for this
technique to work, CCSR needs to be relocated before the initram memory is
enabled.

Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs
we create now for relocating CCSR are deleted after the relocation is finished.
cpu_init_early_f() will still need to create a TLB for CCSR (at the new
location) for normal U-Boot purposes.  This is done to keep the impact to
existing U-Boot code minimal and to better isolate the CCSR relocation code.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Timur Tabi
e46fedfeb2 powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW
macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS.
This is necessary for the assembly-language code that relocates CCSR, since
the assembler does not understand 64-bit constants.

CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the
CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it
should not be defined in a board header file.  Similarly,
CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so
it should also not be defined in the board header file.

CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that
CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT,
and so CCSR will not be relocated.

Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot
builds (e.g. NAND) are required to relocate CCSR only during the last stage
(i.e. the "real" U-Boot).  All other stages should define
CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated.

README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:04 -05:00
Kumar Gala
b6c3722dfa powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:03 -05:00
Ramneek Mehresh
1b719e6654 powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
Add UTMI and ULPI PHY support for USB controller on qoriq series of
processors with internal UTMI PHY implemented, for example P1010/P1014
 - Use both getenv() and hwconfig to get USB phy type till getenv()
   is depricated
 - Introduce CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY to specify if soc
   has internal UTMI phy

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:03 -05:00
Wolfgang Denk
1d5e7fb403 Prepare v2011.09
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-09-29 21:11:15 +02:00
Linus Walleij
94acfed1ae ARM: versatile: delete split_by_variant.sh
Since commit d388298a59 by
Stefano Babic this file is no longer needed so delete it.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Loïc Minier <loic.minier@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-09-28 21:41:22 +02:00
Wolfgang Denk
0dcfb0fcb8 Revert "phylib: remove a couple of redundant code lines"
This reverts commit 041c542219.

The lines removed by this commit weren't redundant. The logic is (and
probably should be better commented):

Find the intersection of the advertised capabilities of both sides of
the link (lpa).
From that intersection, find the highest capability we can run at
(that will be the negotiated link).

Now imagine that the intersection (lpa) is (LPA_100HALF | LPA_10FULL).

The code will now set phydev->speed to 100, and phydev->duplex to 1,
but this link does not support 100FULL.

Kudos to Andy Fleming <afleming@gmail.com> for binging this to
attention and for the explanation.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-09-28 21:02:43 +02:00
Wolfgang Denk
ff4dea0383 doc/README.scrapyard: Update board removal commit IDs
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-09-28 20:42:00 +02:00
Wolfgang Denk
b20a91d81f Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  ARM: remove broken "ixdp425" and "ixpdg425" boards
2011-09-28 20:38:21 +02:00
Albert ARIBAUD
0ca8eb7137 ARM: remove broken "ixdp425" and "ixpdg425" boards
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Stefan Roese <sr@denx.de>
2011-09-27 08:58:04 +02:00
Marek Vasut
0ed1eb6f55 ASIX: Fix buffer access in asix_get_phy_addr()
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
2011-09-24 19:28:50 +02:00
Wolfgang Denk
279bbbca12 Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  OMAP3: beagle: Fix build warning in beagle.c
2011-09-23 08:23:25 +02:00
Vladimir Zapolskiy
7de17781a4 doc: provide a correct board_init_r definition path
This is a trivial fix in the documentation, which corrects
board_init_r() source reference.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2011-09-23 08:12:28 +02:00
Dirk Behme
513e6fd3eb OMAP3: beagle: Fix build warning in beagle.c
Fix build warning

beagle.c:532: warning: initialization from incompatible pointer type

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
CC: Jason Kridner <jkridner@beagleboard.org>
CC: Koen Kooi <koen@dominion.thruhere.net>
CC: Joel A Fernandes <agnel.joel@gmail.com>
Cc: Greg Turner <gregturner@ti.com>
CC: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Jason Kridner <jkridner@beagleboard.org>
2011-09-22 23:02:08 +02:00
Wolfgang Denk
bc196029f5 Prepare v2011.09-rc2
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-09-22 21:58:05 +02:00
Wolfgang Denk
4e368b5d90 Minor Coding Style Cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-09-22 21:57:35 +02:00
Holger Brunck
6478021f12 km/common: fix bug in IVM mac address access
The MAC address stored in the inventory eeprom begins at offset 1.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Wolfgang Denk <wd@denx.de>
2011-09-21 23:38:41 +02:00
Vadim Bendebury
3f96ee3347 sf: fix debug format string warning
On some systems, we get a warning when %lu is used with size_t's, so
use the correct format string.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-09-21 23:05:15 +02:00
Mike Frysinger
ff25d32c25 net: turn name len check into an assert
The new sanity check introduces a printf warning for some systems:
	eth.c:233: warning: format '%zu' expects type 'size_t', but argument 3 has type 'int'

Rather than tweak the format string, use the new assert() helper instead.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-09-21 23:04:34 +02:00
Mike Frysinger
fc77086cf2 ignore soc asm-offsets.s
Recent commit a4814a69d3 cleaned up generation of
asm-offsets.s for SoC dirs, but missed adding it to the ignore
list which makes it show up in `git status`.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-09-21 23:02:46 +02:00
Wolfgang Denk
fc3d29761e Drop bogus BOOTFLAG_* definitions
There is no code anywhere that references BOOTFLAG_* so remove these
defines.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
2011-09-20 13:18:07 +02:00
Peter Korsgaard
7aabad2804 net/bootp.c: fix tftp load if autoload environment var isn't set
Commit 093498669 (Put common autoload code into auto_load() function)
broke handling of autoload environment variable not being set.
The bootp/dhcp code will just keep on requesting IP address forever
and never start TFTP download.

Fix it by moving TftpStart() outside the conditional like it was before.

Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
2011-09-19 23:25:08 +02:00
Stefan Roese
226502e01b ppc4xx: Flush dcache after DDR2 autocalibration with caches on
Flush the dcache before removing the TLB with caches enabled.
Otherwise this might lead to problems later on, e.g. while booting
Linux (as seen on ICON-440SPe).

Signed-off-by: Stefan Roese <sr@denx.de>
2011-09-19 11:51:21 +02:00
Weirich, Bernhard
25fb02abdf Fix incorrect array size of phy settings for 405EX
Change bd_t->bi_phy* arrays from 1 to 2 for PPC405EX since
405EX has 2 ethernet interfaces.

Signed-off-by: Bernhard Weirich <bernhard.weirich@riedel.net>
Signed-off-by: Stefan Roese <sr@denx.de>
2011-09-19 11:51:21 +02:00
Sandeep Paulraj
56fa45d581 DA830: Fix Build Warning
This commit fixes a build warning in the DA830 EVM build

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13 22:24:24 +02:00
Jason Kridner
2d3be7c456 led: remove camel casing of led identifiers globally
Result of running the following command to address Wolfgang's
comment about camel case:

for file in `find . | grep '\.[chS]$'`; do perl -i -pe
's/(green|yellow|red|blue)_LED_(on|off)/$1_led_$2/g' $file; done

Discussion:
http://patchwork.ozlabs.org/patch/84988/

Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13 08:30:52 +02:00
Aneesh V
43de24fdc7 omap4: fix pad configuration settings for SDP and Panda
omap4: fix pad configuration settings for SDP and Panda

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sebastien Jan <s-jan@ti.com>
Signed-off-by: David Anders <x0132446@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13 08:25:16 +02:00
Aneesh V
4ecfcfaa9e omap4: IO settings
Tuning some IO settings for better performance and power.
And consolidate all such IO settings at one place.

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13 08:25:16 +02:00
Aneesh V
025bc4254b omap4: make SDRAM init work for ES1.0 silicon
SDRAM init was not working on ES1.0 due to a programming
error. A pointer that was passed by value to a function
was set in function emif_get_device_details(), but the effect
wouldn't be seen in the calling function. The issue came
out while testing for ES1.0 because ES1.0 doesn't have any
SDRAM chips connected to CS1

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13 08:25:15 +02:00
Aneesh V
16dc702f24 omap4: factor out common part from board config headers
Factor out common parts from omap4_sdp4430.h and omap4_panda.h
into a new file omap4_common.h

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13 08:25:15 +02:00
Sanjeev Premi
84c3b63129 omap: gpio: Adapt board files to use generic API
This patch contains updates the sources in the board files
to use the generic API.

Signed-off-by: Sanjeev Premi <premi@ti.com>
2011-09-13 08:25:15 +02:00
Sanjeev Premi
3b690ebbbf omap: gpio: generic changes after changing API
This patch contains the generic changes required after
change to generic API in the previous patch.

Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13 08:25:15 +02:00
Sanjeev Premi
81bdc155c7 omap: gpio: Use generic API
Convert all OMAP specific functions to use the common API
definitions in include/asm/gpio.h. In the process, made
few additional changes:
 - Use -EINVAL consistently. -1 was used in many places.
 - Removed one-liner static functions that were used only
   once. Replaced the content as necessary.
 - Combines implementation of functions omap_get_gpio_dataout()
   and omap_get_gpio_datain(). To do so, new static function
   _get_gpio_direction() was added.

Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-13 08:25:15 +02:00
Sandeep Paulraj
205c065890 OMAP3 Beagle: Minor config cleanup
This patch removes a hardcoded MAC address

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-12 17:40:48 +02:00
Nagabhushana Netagunte
11a6fb7974 da830: modify the MEMTEST start and end address
Modify the MEMTEST start and end address. The memtest range was overlapping the
CONFIG_SYS_LOAD_ADDR which causes the uImage to be corrupt.Also, modify the
size for which mtest is run to 32MB from 16MB.

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-12 17:40:48 +02:00
Nagabhushana Netagunte
516420aa93 da830: enable SPI flash boot mode
Enable SPI flash boot mode in configuration file as default.
With the introduction of 456MHz part, SPI operating frequency
will increase and at this frequency SPI does not work correctly.
Hence reduce the default SPI speed to 30MHz from 50MHz.

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-12 17:40:48 +02:00
Nagabhushana Netagunte
c0eee7778a da830: modify the U-Boot prompt string
Modify U-boot promt string from 'DA830-evm >' to 'U-Boot >' as
there are many variants of da830 based boards which have diffrent
names such as L137, AM1707 etc.

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2011-09-12 17:40:48 +02:00