Commit Graph

25 Commits

Author SHA1 Message Date
Simon Glass
c17c422854 x86: link: Add build options for SPL
If SPL is used we want to use the generic SPL framework and boot from SPI
via a board-specific means. Add these options to the board config file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-02-07 13:11:04 +08:00
Bin Meng
d21d05f19a x86: Move CONFIG_ENV_IS_IN_SPI_FLASH to x86-common.h
Since all x86 boards use spi flash as its bootloader storage media,
it makes sense to make CONFIG_ENV_IS_IN_SPI_FLASH a common option.
So far only minnowmax board does not support it so undefine it in
its board configuration file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:48 -06:00
Simon Glass
cc285c565a x86: Move common Chromebook config into a separate file
Since Chromebooks mostly have similar configuration, put it in a common
file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-16 19:27:40 -06:00
Simon Glass
e43ade3749 x86: config: chromebook_link: Enable environment
Enable an environment area.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-24 06:13:46 -07:00
Simon Glass
069f5481ba x86: config: Enable hook for saving MRC configuration
Add a hook to ensure that this information is saved.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-24 06:13:45 -07:00
Bin Meng
657e384af6 x86: Remove CONFIG_DISPLAY_CPUINFO in chromebook_link.h
CONFIG_DISPLAY_CPUINFO is already defined in x86-common.h, so remove
it to avoid duplication.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:05 -08:00
Bin Meng
ade8127a79 x86: Make chromebook_link the default board for coreboot
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.

Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.

To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86
define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:04 -08:00
Bin Meng
24ef04280c x86: Move CONFIG_SYS_CAR_xxx to Kconfig
Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
we don't need them in the board configuration file thus the same
board configuratoin file can be used to build both coreboot version
and bare version.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:04 -08:00
Bin Meng
8cb20ccc34 x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:03 -08:00
Bin Meng
41702bac01 x86: Rename coreboot-serial to x86-serial
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:08 -07:00
Bin Meng
63faf2507d x86: Include FSP and CMC binary in the u-boot.rom build rules
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:07 -07:00
Bin Meng
8c5224c9f5 x86: Use consistent name XXX_ADDR for binary blob flash address
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:07 -07:00
Simon Glass
22e131ca00 x86: chromebook_link: Enable the Chrome OS EC
Enable the Chrome OS EC so that it can be used from U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:17 -07:00
Simon Glass
a6fa83f0e7 x86: chromebook_link: Enable the x86 emulator
Enable this so that it can be used instead of native execution if desired.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:17 -07:00
Simon Glass
62d0c5e153 x86: config: Enable video support for chromebook_link
Now that we have the required drivers, enable video support with a suitable
option ROM.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
1ccd452b07 x86: config: Enable SPI for chromebook_link
Enable SPI so that the SPI flash can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
79b303467a x86: config: Enable USB on link
Enable USB support on link - there are two EHCI ports available.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:02 -07:00
Simon Glass
4896f4acc8 x86: dts: Add SATA settings for link
Add the requires settings to enable SATA on link.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
b6b4a0ec55 x86: config: Enable plug-and-play for link PCI
Enable this option so that we can configure the available PCI devices. Also
make sure that PCI is available early after relocation as we use it for
several other subsystems.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:00 -07:00
Simon Glass
65990d5680 x86: Remove board_early_init_r()
This function is not needed. Remove it to improve the generic init sequence
slightly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:33:59 -07:00
Simon Glass
65dd74a674 x86: ivybridge: Implement SDRAM init
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.

SDRAM init works by setting up various parameters and calling the MRC. This
in turn does some sort of magic to work out how much memory there is and
the timing parameters to use. It also sets up the DRAM controllers. When
the MRC returns, we use the information it provides to map out the
available memory in U-Boot.

U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
generally contiguous, and anyway some RAM may be above 4GB which doesn't
work in 32-bit mode. So we relocate to the top of the largest block of
RAM we can find below 4GB. Memory above 4GB is accessible with special
functions (see physmem).

It would be possible to build U-Boot in 64-bit mode but this wouldn't
necessarily provide any more memory, since the largest block is often below
4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
kernels directly so this does not pose a limitation in that area. Also there
are probably parts of U-Boot that will not work correctly in 64-bit mode.
The MRC is one.

There is some work remaining in this area. Since memory init is very slow
(over 500ms) it is possible to save the parameters in SPI flash to speed it
up next time. Suspend/resume support is not fully implemented, or at least
it is not efficient.

With this patch, link boots to a prompt.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
437c2b7cd0 x86: chromebook_link: Enable GPIO support
Enable GPIO support and provide the required GPIO setup information to
the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
6e5b12b614 x86: ivybridge: Enable PCI in early init
Enable PCI so we can access devices that need to be set up before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00
Simon Glass
fce7b27683 x86: Build a .rom file which can be flashed to an x86 machine
On x86 machines U-Boot needs to be added to a large ROM image which is
then flashed onto the target board. The ROM has a particular format so it
makes sense for U-Boot to build this image automatically. Unfortunately
it relies on binary blobs so we cannot require this for the default
build as yet.

Create a u-boot.rom output file for this purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00
Simon Glass
8ef07571a0 x86: Add chromebook_link board
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.

This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00