- Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch)
- Armada 8k: Use ATF serdes init instead of the "old" U-Boot version
(Baruch)
- Minor update to Octeon TX/TX2 defconfig (Stefan)
common:
- Add support for 64bit loadables from SPL
xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format
microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot
zynq:
- Add support for Zturn V5
zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling
versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power
zynq-sdhci:
- Add support for tap delay programming
zynq-spi/zynq-qspi:
- Use clock framework for getting clocks
xilinx-spi:
- Fix some code issues (unused variables)
serial:
- Check return value from clock functions in pl01x
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Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.01-v2
common:
- Add support for 64bit loadables from SPL
xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format
microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot
zynq:
- Add support for Zturn V5
zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling
versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power
zynq-sdhci:
- Add support for tap delay programming
zynq-spi/zynq-qspi:
- Use clock framework for getting clocks
xilinx-spi:
- Fix some code issues (unused variables)
serial:
- Check return value from clock functions in pl01x
Maxime mentioned that he feels not having the time to be an Allwinner
maintainer anymore. Take over from him.
Maxime, many thanks for your great work in the past! I hope I can still
relay the occasional technical question to you in the future.
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Based on Linux kernel commit fc256f5789cb ("mtd: nand: pxa3xx: enable
NAND controller if the SoC needs it"). This commit adds support for the
Armada 8040 nand controller.
The kernel commit says this:
Marvell recent SoCs like A7k/A8k do not boot with NAND flash
controller activated by default. Enabling the controller is a matter
of writing in a system controller register that may also be used for
other NAND related choices.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Move board_fit_config_name_match() from Zynq/ZynqMP to common location.
This change will open a way to use it also by Microblaze and Versal.
Through this function there is a way to handle images with multiple DTBs.
For now match it with DEVICE_TREE as is done for Zynq.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove setting tapdelays for different speeds separately. Instead use
the ITAP and OTAP delay values which are read from the device tree.
If the DT does not contain tap delay values, the predefined values
will be used for the same.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Fix the condition to set UHS timings for speeds upto HS200.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
The kfree() call is unreachable, and is not needed. Remove this call and
the fail_disable_clk label.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Use the generic DT code to find the device compatible property for us.
This makes the driver look more like other current drivers. It also make
it easier to add support for other variants like Armada 8K in a future
commit.
Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Align node properties to kernel dts node.
The change of compatible property does not affect any currently
supported board.
Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Align node properties to kernel dts node.
Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility
with the current driver.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Enable the now included network drivers in the currently supported
Marvell Octeon TX & TX2 boards.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
It helps ATF to determine who called power on function (U-boot/Linux).
The corresponding ATF code was added in this commit:
mvebu: cp110: avoid pcie power on/off sequence when called from Linux
55df84f974
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Replace the comphy initialization for PCIe with appropriate SMC call, so
the firmware will perform appropriate comphy initialization.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Replace all comphy initialization with appropriate smc calls. It will
result with triggering synchronous exception that is handled by Secure
Monitor code in EL3. Then the Secure Monitor code will dispatch each smc
call (by parsing the smc function identifier) and triggers appropriate
comphy initialization.
This patch reworks serdes handling for: SATA, SGMII, HS-SGMII and SFI
interfaces.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Tests tests run the three mux subcommands: list, select, and deselect,
and verify that the commands do what we expect.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This command lets the user list, select, and deselect mux controllers
introduced with the mux framework on the fly. It has 3 subcommands:
list, select, and deselect.
List: Lists all the mux present on the system. The muxes are listed for
each chip. The chip is identified by its device name. Each chip can have
a number of mux controllers. Each is listed in sequence and is assigned
a sequential ID based on its position in the mux chip. It lists details
like ID, whether the mux is currently selected or not, the current
state, the idle state, and the number of states.
A sample output would look something like:
=> mux list
a-mux-controller:
ID Selected Current State Idle State Num States
0 no unknown as-is 0x4
1 no 0x2 0x2 0x10
2 no 0x73 0x73 0x100
another-mux-controller:
ID Selected Current State Idle State Num States
0 no 0x1 0x1 0x4
1 no 0x2 0x2 0x4
Select: Selects a given mux and puts it in the specified state. This
subcommand takes 3 arguments: mux chip, mux ID, state to set
the mux in. The arguments mux chip and mux ID are used to identify which
mux needs to be selected, and then it is selected to the given state.
The mux needs to be deselected before it can be selected again in
another state. The state should be a hexadecimal number.
For example:
=> mux list
a-mux-controller:
ID Selected Current State Idle State Num States
0 no 0x1 0x1 0x4
1 no 0x1 0x1 0x4
=> mux select a-mux-controller 0 0x3
=> mux list
a-mux-controller:
ID Selected Current State Idle State Num States
0 yes 0x3 0x1 0x4
1 no 0x1 0x1 0x4
Deselect: Deselects a given mux and puts it in its idle state. This
subcommand takes 2 arguments: the mux chip and mux ID to identify which
mux needs to be deselected. So in the above example, we can deselect mux
0 using:
=> mux deselect a-mux-controller 0
=> mux list
a-mux-controller:
ID Selected Current State Idle State Num States
0 no 0x1 0x1 0x4
1 no 0x1 0x1 0x4
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Provide tests to check the behavior of the multiplexer framework.
Two sets of tests are added. One is using an emulated multiplexer driver
that can be used to test basic functionality like select, deselect, etc.
The other is using the mmio mux which adds tests specific to it.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The memory is close to full and adding a syscon node in test.dts makes
it go over the limit and makes malloc() fail on startup.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a driver for mmio-based syscon multiplexers controlled by
bitfields in a syscon register range.
This is heavily based on the linux mmio-mux driver.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
This will probe the multiplexer devices that have a "u-boot,mux-autoprobe"
property. As a consequence they will be put in their idle state.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Add a new subsystem that handles multiplexer controllers. The API is the
same as in Linux.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
[trini: Update some error calls to use different functions or pass
correct arguments]
Signed-off-by: Tom Rini <trini@konsulko.com>
A software RTC driver is supplied for UEFI SCT testing.
The following UEFI related bugs are fixed:
* correct handling of daylight saving time in GetTime() and SetTime()
* handling of the gd register in function tracing on RISC-V
* disable U-Boot devices in ExitBootServices()
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Merge tag 'efi-2021-01-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2021-01-rc2
A software RTC driver is supplied for UEFI SCT testing.
The following UEFI related bugs are fixed:
* correct handling of daylight saving time in GetTime() and SetTime()
* handling of the gd register in function tracing on RISC-V
* disable U-Boot devices in ExitBootServices()
The log command has led to NULL dereferences if an unknown category name
name was used due to missing entries in the list of category names.
Add compile time checks for the array sizes of log_cat_name and
log_lvl_name to avoid future mishaps.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adjust the SetTime() and GetTime() runtime services to correctly convert
the daylight saving time information when communicating with the RTC.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
U-Boot Driver Model is supposed to remove devices with either
DM_REMOVE_ACTIVE_DMA or DM_REMOVE_OS_PREPARE flags set, before exiting.
Our bootm command does that by explicitly calling calling
"dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);" and we also disable any
USB devices.
The EFI equivalent is doing none of those at the moment. As a result
probing an fTPM driver now renders it unusable in Linux. During our
(*probe) callback we open a session with OP-TEE, which is supposed to
close with our (*remove) callback. Since the (*remove) is never called,
once we boot into Linux and try to probe the device again we are getting
a busy error response. Moreover all uclass (*preremove) functions won't
run.
So let's fix this by mimicking what bootm does and disconnect devices
when efi_exit_boot_services() is called.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Order header files according to https://www.denx.de/wiki/U-Boot/CodingStyle
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
An UEFI application may change the value of the register that gd lives in.
But some of our functions like get_ticks() access this register. So we
have to set the gd register to the U-Boot value when entering a trace
point and set it back to the application value when exiting the trace
point.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
On a board without hardware clock this software real time clock can be
used. The build time is used to initialize the RTC. So you will have
to adjust the time either manually using the 'date' command or use
the 'sntp' to update the RTC with the time from a network time server.
See CONFIG_CMD_SNTP and CONFIG_BOOTP_NTPSERVER. The RTC time is
advanced according to CPU ticks.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Provide a constant U_BOOT_EPOCH with the number of seconds since
1970-01-01. This constant can be used to initialize a software
real time clock until it is updated via the 'sntp' command.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Provide a unit test checking that a continuation message will use the same
log level and log category as the previous message.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Some drivers use macro pr_cont() for continuing a message sent via printk.
Hence if we want to convert printk messaging to using the logging system,
we must support continuation of log messages too.
As pr_cont() does not provide a message level we need a means of
remembering the last log level.
With the patch a pseudo log level LOGL_CONT as well as a pseudo log
category LOGC_CONT are introduced. Using these results in the application
of the same log level and category as in the previous log message.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Replace the static variable processing_msg by a field in the global data.
Make the field bool at it can only be true or false.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
With disabled legacy VIDEO option CONSOLE_MUX is not auto-selected
any more, re-enable it.
Fixes: 9dec5a0ea1 ("nokia_rx51: disable obsolete VIDEO config")
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
Define default values for input and output clock phase delays for
Versal. Also define functions for setting tapdelays based on these
clock phase delays.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Define and use functions for setting input and output tapdelays
based on clk phase delays.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Define input and output clock phase delays with pre-defined values.
Define arasan_sdhci_clk_data type structure and add it to priv
structure and store these clock phase delays in it.
Read input and output clock phase delays from dt. If these values are
not passed through dt, use pre-defined values.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Just group macros below headers. Other patches will be using this location
too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Define timing macro's for all the available speeds of mmc. This is
done similar to linux. Replace speed macro's used with these new timing
macro's wherever applicable.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This reverts commit 942b5fc032.
This is partial revert of the above commit.
mmc_of_parse() is reading no-1-8-v from device tree and if set,
it is clearing the UHS speed capabilities of cfg->host_caps.
cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 |
MMC_MODE_HS400 | MMC_MODE_HS400_ES);
This is still missing to clear UHS speeds like SDHCI_SUPPORT_SDR104,
SDHCI_SUPPORT_SDR50 and SDHCI_SUPPORT_DDR50.
Even if we clear the flags SDHCI_SUPPORT_XXX in mmc_of_parse(),
these speed flags are getting set again in cfg->host_caps in
sdhci_setup_cfg().
The reason for this is, SDHCI_SUPPORT_XXX flags are cleared
only if controller is not capable of supporting MMC_VDD_165_195 volts.
if (caps & SDHCI_CAN_VDD_180)
cfg->voltages |= MMC_VDD_165_195;
if (!(cfg->voltages & MMC_VDD_165_195))
caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
SDHCI_SUPPORT_DDR50);
It means "no-1-8-v", which is read from DT is not coming in to effect.
So it is better we keep the host quirks(SDHCI_QUIRK_NO_1_8_V) to
clear UHS speeds based on no-1-8-v from device tree.
Hence revert the functionality related to no-1-8-v only, rest is fine
in the patch.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add function description for zynq_qspi_init_hw and zynq_qspi_chipselect.
Fix zqspi to priv in function descriptions.
Change the description of priv as pointer to zynq_qspi_priv structure.
Fix other function descriptions to kernel-doc style.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use tabs to be aligned with the rest of the code.
Fixes: 658df8bd94 ("mtd: spi-nor-core: Add octal mode support")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Call generic board_late_init_xilinx() to be aligned with the rest of xilinx
platforms. Also getting rid of initrd_high/fdt_high and use
bootm_low/boot_size instead.
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
