This setup is a bit special as Linux kernel (4.19) is not supporting
in-kernel NFS rootfs mount and Distributed Switch Architecture (DSA)
operation.
For that reason it was necessary to provide a bootarg to allow userspace
enable it afterwards if needed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After i.MX5's EHCI conversion to DM, the CONFIG_MXC_USB_PORT is not needed
anymore and should be removed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit converts i.MX5's EHCI USB host driver to driver model (DM_USB).
It is a straightforward conversion (to reuse as much code as possible),
based on ehci-mx6.c code.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
As EHCI on i.MX5 has been converted to driver model, the board specific
code, necessary for VBUS USB power supply setup is not needed anymore.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit enables the support for K&P's HSC|DDC imx53 based boards.
It was also necessary to provide device tree description for regulators
to avoid board specific code definition.
The GPIO pin description responsible for VBUS control has been moved from
"hog" group to usbh1 dedicated one.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This code has been ported from Linux kernel - tag v5.1-rc2.
The difference from the kernel is the removal of:
fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;
properties, which are not needed for correct u-boot operation (as PHY
setup is done in ehci-mx5.c file itself).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After unification of the rootfs for both HSC and DDC devices, only one,
common wic file is necessary - without the distinction of specific board.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
In this commit the esdhc3 controller is enabled as well as it is remaped
to mmc0 to not break legacy code.
The pinctrl setup (e.g. 0x1e4) is the same as one from in-board file
definition.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
After commit efd0b79106 ("eth: dm: fec: Add gpio phy reset binding")
the in-board file definition of ETH PHY reset can be removed.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
with u-boot,dm-spl added for imx8qx-pm node, and SPL_SIMPLE_BUS enabled,
the bind and probe code in board file could be removed.
Also we need to enlarge SYS_MALLOC_F_LEN to avoid calloc fail.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Some variations of the imx6q_logic board have eMMC instead of
NAND. Rather than creating a separate defconfig, this patch
adds the ability to read/write to eMMC (mmc 0:1) when NAND
doesn't exist.
Signed-off-by: Adam Ford <aford173@gmail.com>
This adds an extra, optional environmental variable called
'optargs' which if enabled allow additional parameters to be
passed to the kernel (ie, quiet, cma=128M, etc.)
Each script that setups the bootargs will just append this.
Signed-off-by: Adam Ford <aford173@gmail.com>
- Add and enable brcmnand driver on a number of relevant platforms.
Also add and enable LED drivers on more bcm platforms.
- Various ARMv8 fixes/improvements, including extending PSCI
functionality.
- fs_loader improvments
- Various FIT/SPL improvements
- PCI bugfixes
- Poplar platform ethernet support
- MediaTek MMC improvements
- Android boot improvements
According to Android image format [1], kernel image resides at 1 page
offset from the boot image address. Grab the magic number from there
and allow U-Boot to handle LZ4-compressed KNL binaries instead of
hardcoding compression type to IH_COMP_NONE. Other compression types,
if needed, can be added later.
Tested on H3ULCB-KF using the image detailed in [2].
[1] Excerpt from include/android_image.h
+-----------------+
| boot header | 1 page
+-----------------+
| kernel | n pages
+-----------------+
| ramdisk | m pages
+-----------------+
| second stage | o pages
+-----------------+
[2] => iminfo 4c000000
## Checking Image at 4c000000 ...
Android image found
kernel size: 85b9d1
kernel address: 48080000
ramdisk size: 54ddbc
ramdisk addrress: 4a180000
second size: 0
second address: 48000800
tags address: 48000100
page size: 800
os_version: 1200012a (ver: 0.9.0, level: 2018.10)
name:
cmdline: buildvariant=userdebug
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
If CONFIG_UNIT_TEST is enabled we should enable the individual tests by
default to ensure good test coverage.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This fixes relaction isses with the PSCI_TABLE entries in
the psci_32_table and psci_64_table.
When using 32-bit adress pointers relocation was not being applied to
the tables, causing PSCI handlers to point to the un-relocated code
area. By using 64-bit data relocation is properly applied. The
handlers are thus in the "secure data" area, which is protected by
/memreserve/ in the FDT.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
The cache flush of the kernel load area needs to be aligned outward to
the DMA cache alignment. The operations are simpler if we think of this
as aligning the start down, ALIGN_DOWN(load, ARCH_DMA_MINALIGN), and
aligning the end up, ALIGN(load_end, ARCH_DMA_MINALIGN), and then find
the length of the flushed region by subtracting the former from the
latter.
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
When using memalign() in a scenario where U-Boot is configured for full
malloc support with simple malloc not explicitly enabled and before the
full malloc support is initialized, a memory block is being allocated
and returned without the alignment parameter getting honored.
Fix this issue by replacing the existing memalign pre-full malloc init
logic with a call to memalign_simple() this way ensuring proper alignment
of the returned memory block.
Fixes: ee038c58d5 ("malloc: Use malloc simple before malloc is fully initialized in memalign()")
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
This patch adds a short message to the SPL NAND loader, which displays
the source and destinations addresses including the size of the
loaded image, like this:
U-Boot SPL 2019.04-rc3-00113-g486efd8aaf (Mar 15 2019 - 14:18:02 +0100)
Trying to boot from NAND
Loading U-Boot from 0x00040000 (size 0x000a0000) to 0x22900000
I find this message quite helpful - hopefully others do so as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add support for MediaTek MT8516 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add the implementation for the CLK_GATE_SETCLR_INV and
CLK_GATE_NO_SETCLR flags.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
We either need to use IS_ENABLED(CONFIG_FOO) or CONFIG_IS_ENABLED(FOO).
IS_ENABLE(FOO) will always return false.
This commit fixes the comparison by using the CONFIG_IS_ENABLED(FOO)
syntax.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Some MediaTek SoC need an additional clock "source_cg". Enable
this new clock. We reuse the same clock name as in the kernel.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
The 'phy' reset of gmac device in kernel device tree is not generic
enough for u-boot to use, so we need to overwrite the 'resets' property
as needed. With this device tree fixup and poplar_defconfig changes,
Ethernet starts working on Poplar board.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
It adds the driver for HIGMACV300 Ethernet controller found on HiSilicon
SoCs like Hi3798CV200. It's based on a downstream U-Boot driver, but
quite a lot of code gets rewritten and cleaned up to adopt driver model
and PHY API.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
It adds a Driver Model compatible reset driver for HiSlicon platform.
The driver implements a custom .of_xlate function, and uses .data field
as reset register offset and .id field as bit shift.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Some reset controllers support different polarities for reset operation,
so let's add a polarity field into struct reset_ctl.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added
as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale
with the number of DRAM banks, otherwise we will end up with too little
space in the hose->regions array to store all system memory regions.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Make sure that we don't overflow the hose->regions array, otherwise we
would end up overwriting the hose->region_count field and cause mayhem
to ensue. Also print an error message when we'd be overflowing because
it indicates that there aren't enough regions available and the number
needs to be increased.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the migration to DM in SPL and the DT support, the
old legacy code is no longer neaded, so this patch removes it
Signed-off-by: Adam Ford <aford173@gmail.com>
