CPLD 2.2 removed board watch dog support due to the limitation of CPLD
capacity after adding all the requested features, such as switch overriding.
There is no pin-compatible upgrade part available for current PCB design.
So remove codes related to it.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
According to CPLD 2.2, the default configuration is changed, so updated the
description of CPLD command, otherwise it will confusing.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CPLD 2.0 provides a new register which bit[0] is set to '1' will reset
board with initializing the CPLD registers to default values. And add
bit[6] of register at offset 0x5 to use to enable flash bank selection.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P2041RDB Specification:
-----------------------
Memory subsystem:
* 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
* 128 Mbyte NOR flash single-chip memory
* 256 Kbit M24256 I2C EEPROM
* 16 Mbyte SPI memory
* SD connector to interface with the SD memory card
Ethernet:
* dTSEC1: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC2: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC3: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC4: connected to the Vitesse RGMII PHY (VSC8641)
* dTSEC5: connected to the Vitesse RGMII PHY (VSC8641)
PCIe:
* Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1
* Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2
SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors
USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces
I2C:
* I2C1: Real time clock, Temperature sensor, Memory module
* I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
