mirrors/u-boot
0
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2024-11-26 13:44:29 +08:00
Code Issues Packages Projects Releases Wiki Activity

Add support for 256 MB SDRAM on CPU87

Browse Source 
Patch by Josef Wagner, 25 Nov 2005
This commit is contained in:
Wolfgang Denk 2006-07-22 21:45:49 +02:00
parent 135ae0062f
commit fd27996dac
3 changed files with 40 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
CHANGELOG
View File

@ -2,6 +2,9 @@
Changes since U-Boot 1.1.4:
======================================================================
* Add support for 256 MB SDRAM on CPU87
Patch by Josef Wagner, 25 Nov 2005
* Add configuration for cam5200 board (based on TQM5200S).
* More code cleanup

24
board/cpu87/cpu87.c
View File

@ -197,7 +197,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
*/
int checkboard (void)
{
printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV);
printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV & 0x7f);
return 0;
}
@ -280,7 +280,7 @@ long int initdram (int board_type)
volatile memctl8260_t *memctl = &immap->im_memctl;
#ifndef CFG_RAMBOOT
ulong size8, size9;
ulong size8, size9, size10;
#endif
long psize;
@ -294,17 +294,25 @@ long int initdram (int board_type)
*/
size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
(uchar *) CFG_SDRAM_BASE);
if (size8 < size9) {
psize = size9;
printf ("(60x:9COL) ");
} else {
size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL,
(uchar *) CFG_SDRAM_BASE);
psize = max(size8,max(size9,size10));
if (psize == size8) {
psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
printf ("(60x:8COL) ");
}
} else if (psize == size9){
psize = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
(uchar *) CFG_SDRAM_BASE);
printf ("(60x:9COL) ");
} else
printf ("(60x:10COL) ");
#endif /* CFG_RAMBOOT */

24
include/configs/CPU87.h
View File

@ -455,7 +455,7 @@
#define CFG_MIN_AM_MASK 0xC0000000
/*
* we use the same values for 32 MB and 128 MB SDRAM
* we use the same values for 32 MB, 128 MB and 256 MB SDRAM
* refresh rate = 7.68 uS (100 MHz Bus Clock)
*/
@ -510,6 +510,24 @@
PSDMR_WRC_1C |\
PSDMR_CL_2)
/* SDRAM initialization values for 10-column chips
*/
#define CFG_OR2_10COL (CFG_MIN_AM_MASK |\
ORxS_BPD_4 |\
ORxS_ROWST_PBI1_A4 |\
ORxS_NUMR_13)
#define CFG_PSDMR_10COL (PSDMR_PBI |\
PSDMR_SDAM_A17_IS_A5 |\
PSDMR_BSMA_A13_A15 |\
PSDMR_SDA10_PBI1_A6 |\
PSDMR_RFRC_7_CLK |\
PSDMR_PRETOACT_2W |\
PSDMR_ACTTORW_2W |\
PSDMR_LDOTOPRE_1C |\
PSDMR_WRC_1C |\
PSDMR_CL_2)
/*
* Init Memory Controller:
*
@ -588,9 +606,9 @@
BRx_MS_SDRAM_P |\
BRx_V)
#define CFG_OR2_PRELIM CFG_OR2_9COL
#define CFG_OR2_PRELIM CFG_OR2_8COL
#define CFG_PSDMR CFG_PSDMR_9COL
#define CFG_PSDMR CFG_PSDMR_8COL
#endif /* CFG_RAMBOOT */
/* Bank 3 - Dual Ported SRAM