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ARM: dts: uniphier: add ProXstream2 and PH1-LD6b SoC/board support
Initial version of DTSI for ProXstream2 and PH1-LD6b and DTS for PH1-LD6b reference board. Import from Linux with some adjustments: - Use SPDX-License-Identifier - Add clock-frequency to serial nodes - Drop unusable nodes from -ref.dts While I am here, sort Makefile entries alphabetically. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
parent
10ee0a68d8
commit
f875bbb491
@ -38,9 +38,10 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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tegra210-p2371-0000.dtb \
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tegra210-p2571.dtb
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dtb-$(CONFIG_ARCH_UNIPHIER) += \
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uniphier-ph1-sld3-ref.dtb \
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uniphier-ph1-pro4-ref.dtb \
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uniphier-ph1-ld4-ref.dtb \
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uniphier-ph1-ld6b-ref.dtb \
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uniphier-ph1-pro4-ref.dtb \
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uniphier-ph1-sld3-ref.dtb \
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uniphier-ph1-sld8-ref.dtb
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dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
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zynq-zc706.dtb \
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59
arch/arm/dts/uniphier-ph1-ld6b-ref.dts
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59
arch/arm/dts/uniphier-ph1-ld6b-ref.dts
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@ -0,0 +1,59 @@
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/*
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* Device Tree Source for UniPhier PH1-LD6b Reference Board
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*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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*/
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/dts-v1/;
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/include/ "uniphier-ph1-ld6b.dtsi"
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/include/ "uniphier-ref-daughter.dtsi"
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/ {
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model = "UniPhier PH1-LD6b Reference Board";
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compatible = "socionext,ph1-ld6b-ref", "socionext,ph1-ld6b";
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memory {
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device_type = "memory";
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reg = <0x80000000 0x80000000>;
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};
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chosen {
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bootargs = "console=ttyS0,115200";
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stdout-path = &serial0;
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};
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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};
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};
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&serial0 {
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status = "okay";
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};
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&serial1 {
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status = "okay";
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};
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&serial2 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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/* for U-boot only */
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&serial0 {
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u-boot,dm-pre-reloc;
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};
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31
arch/arm/dts/uniphier-ph1-ld6b.dtsi
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31
arch/arm/dts/uniphier-ph1-ld6b.dtsi
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@ -0,0 +1,31 @@
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/*
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* Device Tree Source for UniPhier PH1-LD6b SoC
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*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+ X11
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*/
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/*
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* PH1-LD6b consists of two silicon dies: D-chip and A-chip.
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* The D-chip (digital chip) is the same as the ProXstream2 die.
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* Reuse the ProXstream2 device tree with some properties overridden.
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*/
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/include/ "uniphier-proxstream2.dtsi"
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/ {
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compatible = "socionext,ph1-ld6b";
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};
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/* UART3 unavilable: the pads are not wired to the package balls */
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&serial3 {
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status = "disabled";
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};
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/*
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* PH1-LD6b and ProXstream2 have completely different packages,
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* which makes the pinctrl driver unshareable.
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*/
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&pinctrl {
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compatible = "socionext,ph1-ld6b-pinctrl", "syscon";
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};
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241
arch/arm/dts/uniphier-proxstream2.dtsi
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241
arch/arm/dts/uniphier-proxstream2.dtsi
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@ -0,0 +1,241 @@
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/*
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* Device Tree Source for UniPhier ProXstream2 SoC
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*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+ X11
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "socionext,proxstream2";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "socionext,uniphier-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <3>;
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};
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};
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clocks {
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arm_timer_clk: arm_timer_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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uart_clk: uart_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <88900000>;
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};
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i2c_clk: i2c_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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extbus: extbus {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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interrupts = <0 33 4>;
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clocks = <&uart_clk>;
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clock-frequency = <88900000>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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interrupts = <0 35 4>;
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clocks = <&uart_clk>;
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clock-frequency = <88900000>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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interrupts = <0 37 4>;
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clocks = <&uart_clk>;
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clock-frequency = <88900000>;
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};
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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interrupts = <0 177 4>;
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clocks = <&uart_clk>;
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clock-frequency = <88900000>;
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};
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58780000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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interrupts = <0 41 4>;
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clocks = <&i2c_clk>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58781000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58781000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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interrupts = <0 42 4>;
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clocks = <&i2c_clk>;
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clock-frequency = <100000>;
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};
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i2c2: i2c@58782000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58782000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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interrupts = <0 43 4>;
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clocks = <&i2c_clk>;
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clock-frequency = <100000>;
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};
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i2c3: i2c@58783000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58783000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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interrupts = <0 44 4>;
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clocks = <&i2c_clk>;
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clock-frequency = <100000>;
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};
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/* chip-internal connection for DMD */
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i2c4: i2c@58784000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58784000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 45 4>;
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clocks = <&i2c_clk>;
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clock-frequency = <400000>;
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};
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/* chip-internal connection for STM */
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i2c5: i2c@58785000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58785000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 25 4>;
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clocks = <&i2c_clk>;
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clock-frequency = <400000>;
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};
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/* chip-internal connection for HDMI */
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i2c6: i2c@58786000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58786000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 26 4>;
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clocks = <&i2c_clk>;
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clock-frequency = <400000>;
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};
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system-bus-controller-misc@59800000 {
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compatible = "socionext,uniphier-system-bus-controller-misc",
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"syscon";
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reg = <0x59800000 0x2000>;
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};
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pinctrl: pinctrl@5f801000 {
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compatible = "socionext,proxstream2-pinctrl", "syscon";
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reg = <0x5f801000 0xe00>;
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};
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timer@60000200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x60000200 0x20>;
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interrupts = <1 11 0xf04>;
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clocks = <&arm_timer_clk>;
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};
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timer@60000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x60000600 0x20>;
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interrupts = <1 13 0xf04>;
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clocks = <&arm_timer_clk>;
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};
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intc: interrupt-controller@60001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x60001000 0x1000>,
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<0x60000100 0x100>;
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};
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};
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};
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/include/ "uniphier-pinctrl.dtsi"
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