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u-boot-imx-20230713

Browse Source 
-------------------
 
 Merge for 2023.10.
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16888
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Merge tag 'u-boot-imx-20230713' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20230713
-------------------

Merge for 2023.10.

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16888
This commit is contained in:
Tom Rini 2023-07-13 20:38:24 -04:00
commit f6da5e9273
162 changed files with 5925 additions and 2075 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/Kconfig
View File

@ -882,7 +882,7 @@ config ARCH_IMX8ULP
select SUPPORT_SPL
select GPIO_EXTRA_HEADER
select MISC
select IMX_SENTINEL
select IMX_ELE
imply CMD_DM
config ARCH_IMX9
@ -894,7 +894,7 @@ config ARCH_IMX9
select SUPPORT_SPL
select GPIO_EXTRA_HEADER
select MISC
select IMX_SENTINEL
select IMX_ELE
imply CMD_DM
config ARCH_IMXRT
@ -912,14 +912,12 @@ config ARCH_MX23
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select MACH_IMX
select PL011_SERIAL
select SUPPORT_SPL
config ARCH_MX28
bool "NXP i.MX28 family"
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select PL011_SERIAL
select MACH_IMX
select SUPPORT_SPL

6
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
View File

@ -128,8 +128,10 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
mxs_spl_console_init();
debug("SPL: Serial Console Initialised\n");
if (!CONFIG_IS_ENABLED(DM_SERIAL)) {
mxs_spl_console_init();
debug("SPL: Serial Console Initialised\n");
}
mxs_power_init();

38
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
View File

@ -41,6 +41,29 @@ static void mxs_power_clock2xtal(void)
&clkctrl_regs->hw_clkctrl_clkseq_set);
}
static void mxs_power_regs_dump(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
debug("ctrl:\t\t 0x%x\n", readl(&power_regs->hw_power_ctrl));
debug("5vctrl:\t\t 0x%x\n", readl(&power_regs->hw_power_5vctrl));
debug("minpwr:\t\t 0x%x\n", readl(&power_regs->hw_power_minpwr));
debug("charge:\t\t 0x%x\n", readl(&power_regs->hw_power_charge));
debug("vddctrl:\t 0x%x\n", readl(&power_regs->hw_power_vdddctrl));
debug("vddactrl:\t 0x%x\n", readl(&power_regs->hw_power_vddactrl));
debug("vddioctrl:\t 0x%x\n", readl(&power_regs->hw_power_vddioctrl));
debug("vddmemctrl:\t 0x%x\n", readl(&power_regs->hw_power_vddmemctrl));
debug("dcdc4p2:\t 0x%x\n", readl(&power_regs->hw_power_dcdc4p2));
debug("misc:\t\t 0x%x\n", readl(&power_regs->hw_power_misc));
debug("dclimits:\t 0x%x\n", readl(&power_regs->hw_power_dclimits));
debug("loopctrl:\t 0x%x\n", readl(&power_regs->hw_power_loopctrl));
debug("sts:\t\t 0x%x\n", readl(&power_regs->hw_power_sts));
debug("speed:\t\t 0x%x\n", readl(&power_regs->hw_power_speed));
debug("battmonitor:\t 0x%x\n",
readl(&power_regs->hw_power_battmonitor));
}
/**
* mxs_power_clock2pll() - Switch CPU core clock source to PLL
*
@ -752,7 +775,19 @@ static void mxs_batt_boot(void)
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
mxs_power_enable_4p2();
if (CONFIG_IS_ENABLED(MXS_PMU_MINIMAL_VDD5V_CURRENT))
setbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_ILIMIT_EQ_ZERO);
if (CONFIG_IS_ENABLED(MXS_PMU_DISABLE_BATT_CHARGE)) {
writel(POWER_CHARGE_PWD_BATTCHRG,
&power_regs->hw_power_charge_set);
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_set);
}
if (CONFIG_IS_ENABLED(MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR))
mxs_power_enable_4p2();
}
/**
@ -1268,6 +1303,7 @@ void mxs_power_init(void)
POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
mxs_power_regs_dump();
early_delay(1000);
}

1
arch/arm/dts/Makefile
View File

@ -1017,6 +1017,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-venice.dtb \
imx8mp-venice-gw74xx.dtb \
imx8mp-venice-gw7905-2x.dtb \
imx8mp-verdin-wifi-dev.dtb \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb \

45
arch/arm/dts/imx28-xea-u-boot.dtsi
View File

@ -12,6 +12,11 @@
*/
#include "imx28-u-boot.dtsi"
/ {
aliases {
/delete-property/ spi1;
/delete-property/ usbphy0;
/delete-property/ usbphy1;
};
apb@80000000 {
bootph-pre-ram;
@ -27,16 +32,47 @@
&clks {
bootph-pre-ram;
status = "disable";
};
&duart {
/delete-property/ clocks;
bootph-pre-ram;
type = <1>; /* TYPE_PL011 */
};
&gpio0 {
bootph-pre-ram;
};
&mac0 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-supply = <&reg_fec_3v3>;
phy-reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <1>;
status = "okay";
fixed-link {
speed = <100>;
full-duplex;
};
};
&pinctrl {
/delete-property/ pinctrl-names;
/delete-property/ pinctrl-0;
bootph-pre-ram;
};
&reg_fec_3v3 {
gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
&ssp0 {
bootph-pre-ram;
};
@ -46,3 +82,12 @@
spi-max-frequency = <40000000>;
bootph-pre-ram;
};
/delete-node/ &ssp2;
/delete-node/ &usb0;
/delete-node/ &usbphy0;
/delete-node/ &usb1;
/delete-node/ &usbphy1;
/delete-node/ &hog_pins_a;
/delete-node/ &hog_pins_tiva;
/delete-node/ &hog_pins_coding;

4
arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
View File

@ -6,6 +6,10 @@
#include "imx8mm-u-boot.dtsi"
/ {
aliases {
spi0 = &flexspi;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;

17
arch/arm/dts/imx8mm-mx8menlo.dts
View File

@ -10,6 +10,7 @@
/ {
model = "MENLO MX8MM EMBEDDED DEVICE";
compatible = "menlo,mx8menlo",
"toradex,verdin-imx8mm-nonwifi",
"toradex,verdin-imx8mm",
"fsl,imx8mm";
@ -250,21 +251,21 @@
/* SODIMM 96 */
MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4
/* CPLD_D[7] */
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x184
/* CPLD_D[6] */
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x184
/* CPLD_D[5] */
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x184
/* CPLD_D[4] */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x184
/* CPLD_D[3] */
MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4
MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x184
/* CPLD_D[2] */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x184
/* CPLD_D[1] */
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x184
/* CPLD_D[0] */
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x184
/* KBD_intK */
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4
/* DISP_reset */

150
arch/arm/dts/imx8mm-verdin-dahlia.dtsi
View File

@ -1,150 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/ {
sound_card: sound-card {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,name = "imx8mm-wm8904";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"Headphone Jack", "MICBIAS",
"IN1L", "Headphone Jack";
simple-audio-card,widgets =
"Microphone", "Headphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
dailink_master: simple-audio-card,codec {
clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
sound-dai = <&wm8904_1a>;
};
simple-audio-card,cpu {
sound-dai = <&sai2>;
};
};
};
/* Verdin SPI_1 */
&ecspi2 {
status = "okay";
};
/* EEPROM on display adapter boards */
&eeprom_display_adapter {
status = "okay";
};
/* EEPROM on Verdin Development board */
&eeprom_carrier_board {
status = "okay";
};
&fec1 {
status = "okay";
};
/* Verdin QSPI_1 */
&flexspi {
status = "okay";
};
/* Current measurement into module VCC */
&hwmon {
status = "okay";
};
&hwmon_temp {
vs-supply = <&reg_1p8v>;
status = "okay";
};
&i2c3 {
status = "okay";
};
/* Verdin I2C_1 */
&i2c4 {
status = "okay";
/* Audio Codec */
wm8904_1a: audio-codec@1a {
compatible = "wlf,wm8904";
AVDD-supply = <&reg_3p3v>;
clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
clock-names = "mclk";
CPVDD-supply = <&reg_3p3v>;
DBVDD-supply = <&reg_3p3v>;
DCVDD-supply = <&reg_3p3v>;
MICVDD-supply = <&reg_3p3v>;
reg = <0x1a>;
#sound-dai-cells = <0>;
};
};
/* Verdin PCIE_1 */
&pcie0 {
status = "okay";
};
&pcie_phy {
status = "okay";
};
/* Verdin PWM_3_DSI */
&pwm1 {
status = "okay";
};
/* Verdin PWM_1 */
&pwm2 {
status = "okay";
};
/* Verdin PWM_2 */
&pwm3 {
status = "okay";
};
/* Verdin I2S_1 */
&sai2 {
status = "okay";
};
/* Verdin UART_3 */
&uart1 {
status = "okay";
};
/* Verdin UART_1 */
&uart2 {
status = "okay";
};
/* Verdin UART_2 */
&uart3 {
status = "okay";
};
/* Verdin USB_1 */
&usbotg1 {
status = "okay";
};
/* Verdin USB_2 */
&usbotg2 {
status = "okay";
};
/* Verdin SD_1 */
&usdhc2 {
status = "okay";
};

97
arch/arm/dts/imx8mm-verdin-dev.dtsi
View File

@ -3,14 +3,13 @@
* Copyright 2022 Toradex
*/
#include "imx8mm-verdin-dahlia.dtsi"
/ {
sound_card: sound-card {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "imx8mm-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",
@ -41,27 +40,121 @@
};
};
/* Verdin SPI_1 */
&ecspi2 {
status = "okay";
};
/* EEPROM on display adapter boards */
&eeprom_display_adapter {
status = "okay";
};
/* EEPROM on Verdin Development board */
&eeprom_carrier_board {
status = "okay";
};
&fec1 {
status = "okay";
};
/* Verdin QSPI_1 */
&flexspi {
status = "okay";
};
/* Current measurement into module VCC */
&hwmon {
status = "okay";
};
&hwmon_temp {
vs-supply = <&reg_1p8v>;
status = "okay";
};
&i2c3 {
status = "okay";
};
&gpio_expander_21 {
status = "okay";
};
/* Verdin I2C_1 */
&i2c4 {
status = "okay";
/* Audio Codec */
nau8822_1a: audio-codec@1a {
compatible = "nuvoton,nau8822";
reg = <0x1a>;
#sound-dai-cells = <0>;
};
};
/* Verdin PCIE_1 */
&pcie0 {
status = "okay";
};
&pcie_phy {
status = "okay";
};
/* Verdin PWM_3_DSI */
&pwm1 {
status = "okay";
};
/* Verdin PWM_1 */
&pwm2 {
status = "okay";
};
/* Verdin PWM_2 */
&pwm3 {
status = "okay";
};
/* Verdin I2S_1 */
&sai2 {
status = "okay";
};
/* Verdin UART_3 */
&uart1 {
status = "okay";
};
/* Verdin UART_1, connector X50 through RS485 transceiver */
&uart2 {
linux,rs485-enabled-at-boot-time;
rs485-rts-active-low;
rs485-rx-during-tx;
status = "okay";
};
/* Verdin UART_2 */
&uart3 {
status = "okay";
};
/* Verdin USB_1 */
&usbotg1 {
disable-over-current;
status = "okay";
};
/* Verdin USB_2 */
&usbotg2 {
disable-over-current;
status = "okay";
};
/* Limit frequency on dev board due to long traces and bad signal integrity */
&usdhc2 {
max-frequency = <100000000>;
status = "okay";
};

8
arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi
View File

@ -56,6 +56,10 @@
&gpio5 {
bootph-pre-ram;
ctrl-sleep-moci-hog {
bootph-pre-ram;
};
};
&i2c1 {
@ -88,6 +92,10 @@
};
};
&pinctrl_ctrl_sleep_moci {
bootph-pre-ram;
};
&pinctrl_i2c1 {
bootph-pre-ram;
};

30
arch/arm/dts/imx8mm-verdin.dtsi
View File

@ -3,8 +3,8 @@
* Copyright 2022 Toradex
*/
#include "dt-bindings/phy/phy-imx8-pcie.h"
#include "dt-bindings/pwm/pwm.h"
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8mm.dtsi"
/ {
@ -56,7 +56,11 @@
hdmi_connector: hdmi-connector {
compatible = "hdmi-connector";
ddc-i2c-bus = <&i2c2>;
/* Verdin PWM_3_DSI (SODIMM 19) */
hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
label = "hdmi";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>;
type = "a";
status = "disabled";
};
@ -95,9 +99,10 @@
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
off-on-delay = <500000>;
off-on-delay-us = <500000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_eth>;
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
@ -134,7 +139,7 @@
enable-active-high;
/* Verdin SD_1_PWR_EN (SODIMM 76) */
gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
off-on-delay = <100000>;
off-on-delay-us = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
regulator-max-microvolt = <3300000>;
@ -183,15 +188,15 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-750000000 {
opp-hz = /bits/ 64 <750000000>;
};
};
@ -358,7 +363,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x25>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
/*
* The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
@ -598,7 +602,7 @@
hdmi_lontium_lt8912: hdmi@48 {
compatible = "lontium,lt8912b";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
pinctrl-0 = <&pinctrl_gpio_10_dsi>;
reg = <0x48>;
/* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
/* Verdin GPIO_10_DSI (SODIMM 21) */
@ -610,7 +614,7 @@
compatible = "atmel,maxtouch";
/*
* Verdin GPIO_9_DSI
* (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
* (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
*/
interrupt-parent = <&gpio3>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
@ -653,9 +657,6 @@
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
assigned-clock-rates = <10000000>, <250000000>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_PHY>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
/* PCIE_1_RESET# (SODIMM 244) */
@ -664,6 +665,7 @@
&pcie_phy {
clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
clock-names = "ref";
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
@ -739,7 +741,6 @@
adp-disable;
dr_mode = "otg";
hnp-disable;
over-current-active-low;
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
srp-disable;
@ -749,7 +750,6 @@
/* Verdin USB_2 */
&usbotg2 {
dr_mode = "host";
over-current-active-low;
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
vbus-supply = <&reg_usb_otg2_vbus>;

17
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
View File

@ -13,6 +13,19 @@
bootph-pre-ram;
};
&eeprom_som {
#address-cells = <1>;
#size-cells = <1>;
eth_mac_address: eth-mac-address@19 {
reg = <0x19 0x06>;
};
};
&fec1 {
nvmem-cells = <&eth_mac_address>;
nvmem-cell-names = "mac-address";
};
&gpio1 {
bootph-pre-ram;
};
@ -68,3 +81,7 @@
&usdhc3 {
bootph-pre-ram;
};
&eeprom_som {
bootph-pre-ram;
};

4
arch/arm/dts/imx8mn-var-som-symphony.dts
View File

@ -56,10 +56,6 @@
};
};
&ethphy {
reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";

18
arch/arm/dts/imx8mn-var-som.dtsi
View File

@ -11,6 +11,10 @@
model = "Variscite VAR-SOM-MX8MN module";
compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
aliases {
eeprom-som = &eeprom_som;
};
chosen {
stdout-path = &uart4;
};
@ -98,11 +102,17 @@
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@4 {
ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
/*
* Deassert delay:
* ADIN1300 requires 5ms.
* AR8033 requires 1ms.
*/
reset-deassert-us = <20000>;
};
};
};
@ -222,6 +232,12 @@
};
};
};
eeprom_som: eeprom@52 {
compatible = "atmel,24c04";
reg = <0x52>;
pagesize = <16>;
};
};
&i2c3 {

2
arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
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@ -185,12 +185,10 @@
&usb3_0 {
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
/delete-property/ power-domains;
};
&usb3_1 {
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
/delete-property/ power-domains;
};
&usb_dwc3_0 {

3
arch/arm/dts/imx8mp-u-boot.dtsi
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@ -44,6 +44,9 @@
&aips3 {
bootph-pre-ram;
spba-bus@30800000 {
bootph-pre-ram;
};
};
&iomuxc {

12
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@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2023 Gateworks Corporation
*/
#include "imx8mp-venice-u-boot.dtsi"
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};

587
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
aliases {
ethernet0 = &eqos;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
gpio-keys {
compatible = "gpio-keys";
key-user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
key-user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key_erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
key-eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
key-tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
};
&A53_0 {
cpu-supply = <&buck3_reg>;
};
&A53_1 {
cpu-supply = <&buck3_reg>;
};
&A53_2 {
cpu-supply = <&buck3_reg>;
};
&A53_3 {
cpu-supply = <&buck3_reg>;
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
pinctrl-0 = <&pinctrl_ethphy0>;
pinctrl-names = "default";
reg = <0x0>;
interrupt-parent = <&gpio3>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
pinctrl-0 = <&pinctrl_gsc>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@6 {
gw,mode = <0>;
reg = <0x06>;
label = "temp";
};
channel@8 {
gw,mode = <3>;
reg = <0x08>;
label = "vdd_bat";
};
channel@16 {
gw,mode = <4>;
reg = <0x16>;
label = "fan_tach";
};
channel@82 {
gw,mode = <2>;
reg = <0x82>;
label = "vdd_vin";
gw,voltage-divider-ohms = <22100 1000>;
};
channel@84 {
gw,mode = <2>;
reg = <0x84>;
label = "vdd_adc1";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@86 {
gw,mode = <2>;
reg = <0x86>;
label = "vdd_adc2";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@88 {
gw,mode = <2>;
reg = <0x88>;
label = "vdd_1p0";
};
channel@8c {
gw,mode = <2>;
reg = <0x8c>;
label = "vdd_1p8";
};
channel@8e {
gw,mode = <2>;
reg = <0x8e>;
label = "vdd_2p5";
};
channel@90 {
gw,mode = <2>;
reg = <0x90>;
label = "vdd_3p3";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@92 {
gw,mode = <2>;
reg = <0x92>;
label = "vdd_dram";
};
channel@98 {
gw,mode = <2>;
reg = <0x98>;
label = "vdd_soc";
};
channel@9a {
gw,mode = <2>;
reg = <0x9a>;
label = "vdd_arm";
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
label = "vdd_gsc";
gw,voltage-divider-ohms = <10000 10000>;
};
};
fan-controller@0 {
compatible = "gw,gsc-fan";
reg = <0x0a>;
};
};
gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
pmic@69 {
compatible = "mps,mp5416";
reg = <0x69>;
regulators {
/* vdd_soc */
buck1 {
regulator-name = "buck1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
/* vdd_dram */
buck2 {
regulator-name = "buck2";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
};
/* vdd_arm */
buck3_reg: buck3 {
regulator-name = "buck3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
/* vdd_1p8 */
buck4 {
regulator-name = "buck4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
/* OUT2: nvcc_snvs_1p8 */
ldo1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
/* OUT3: vdd_1p0 */
ldo2 {
regulator-name = "ldo2";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
/* OUT4: vdd_2p5 */
ldo3 {
regulator-name = "ldo3";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
regulator-boot-on;
};
/* OUT5: vdd_3p3 */
ldo4 {
regulator-name = "ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
};
};
};
/* off-board header */
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
};
};
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/* off-board header */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* off-board header */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
/* off-board */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
non-removable;
status = "okay";
bus-width = <4>;
non-removable;
status = "okay";
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
>;
};
pinctrl_ethphy0: ethphy0grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */
>;
};
pinctrl_gsc: gscgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2023 Gateworks Corporation
*/
#include "imx8mp-venice-gw702x-u-boot.dtsi"
&gpio1 {
app_gpioa {
gpio-hog;
input;
gpios = <13 GPIO_ACTIVE_HIGH>;
line-name = "gpioa";
};
};
&gpio4 {
app_gpiod {
gpio-hog;
input;
gpios = <1 GPIO_ACTIVE_HIGH>;
line-name = "gpiod";
};
app_gpiob {
gpio-hog;
input;
gpios = <4 GPIO_ACTIVE_HIGH>;
line-name = "gpiob";
};
app_gpioc {
gpio-hog;
input;
gpios = <5 GPIO_ACTIVE_HIGH>;
line-name = "gpioc";
};
pci_usb_sel {
gpio-hog;
output-low;
gpios = <26 GPIO_ACTIVE_HIGH>;
line-name = "pci_usb_sel";
};
pci_wdis {
gpio-hog;
output-high;
gpios = <28 GPIO_ACTIVE_HIGH>;
line-name = "pci_wdis#";
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mp.dtsi"
#include "imx8mp-venice-gw702x.dtsi"
#include "imx8mp-venice-gw7905.dtsi"
/ {
model = "Gateworks Venice GW7905-2x i.MX8MP Development Kit";
compatible = "gateworks,imx8mp-gw7905-2x", "fsl,imx8mp";
chosen {
stdout-path = &uart2;
};
};
/* Disable SOM interfaces not used on baseboard */
&eqos {
status = "disabled";
};
&usdhc1 {
status = "disabled";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_usb2_vbus: regulator-usb2-vbus {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb2_en>;
compatible = "regulator-fixed";
regulator-name = "usb2_vbus";
gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
compatible = "regulator-fixed";
regulator-name = "SD2_3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
/* off-board header */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&gpio4 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "gpioa", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio4 {
gpio-line-names =
"", "gpiod", "", "",
"gpiob", "gpioc", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "pci_usb_sel", "",
"pci_wdis#", "", "", "";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
};
};
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* GPS */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* USB1 - Type C front panel SINK port J14 */
&usb3_0 {
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "peripheral";
status = "okay";
};
/* USB2 4-port USB3.0 HUB:
* P1 - USBC connector (host only)
* P2 - USB2 test connector
* P3 - miniPCIe full card
* P4 - miniPCIe half card
*/
&usb3_phy1 {
vbus-supply = <&reg_usb2_vbus>;
status = "okay";
};
&usb3_1 {
fsl,permanently-attached;
fsl,disable-port-power-control;
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
/* microSD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40000040 /* GPIOA */
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000040 /* GPIOD */
MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x40000040 /* GPIOB */
MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x40000040 /* GPIOC */
MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000106 /* PCI_USBSEL */
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x6 /* LEDR */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_pcie0: pciegrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x106
>;
};
pinctrl_reg_usb2_en: regusb2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x6 /* USBHUB_RST# (ext p/u) */
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
};

129
arch/arm/dts/imx8mp-verdin-dahlia.dtsi
View File

@ -1,129 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/* TODO: Audio Codec */
&backlight {
power-supply = <&reg_3p3v>;
};
/* Verdin SPI_1 */
&ecspi1 {
status = "okay";
};
/* EEPROM on display adapter boards */
&eeprom_display_adapter {
status = "okay";
};
/* EEPROM on Verdin Development board */
&eeprom_carrier_board {
status = "okay";
};
&eqos {
status = "okay";
};
&flexcan1 {
status = "okay";
};
&flexcan2 {
status = "okay";
};
/* Verdin QSPI_1 */
&flexspi {
status = "okay";
};
/* Current measurement into module VCC */
&hwmon {
status = "okay";
};
&hwmon_temp {
vs-supply = <&reg_1p8v>;
status = "okay";
};
/* Verdin I2C_2_DSI */
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
/* Verdin I2C_1 */
&i2c4 {
status = "okay";
/* TODO: Audio Codec */
};
/* TODO: Verdin PCIE_1 */
/* Verdin PWM_1 */
&pwm1 {
status = "okay";
};
/* Verdin PWM_2 */
&pwm2 {
status = "okay";
};
/* Verdin PWM_3_DSI */
&pwm3 {
status = "okay";
};
&reg_usdhc2_vmmc {
vin-supply = <&reg_3p3v>;
};
/* TODO: Verdin I2S_1 */
/* Verdin UART_1 */
&uart1 {
status = "okay";
};
/* Verdin UART_2 */
&uart2 {
status = "okay";
};
/* Verdin UART_3, used as the Linux Console */
&uart3 {
status = "okay";
};
/* Verdin USB_1 */
&usb3_0 {
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
/* Verdin USB_2 */
&usb3_1 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
/* Verdin SD_1 */
&usdhc2 {
status = "okay";
};

125
arch/arm/dts/imx8mp-verdin-dev.dtsi
View File

@ -3,8 +3,6 @@
* Copyright 2022 Toradex
*/
#include "imx8mp-verdin-dahlia.dtsi"
/ {
/* TODO: Audio Codec */
@ -12,7 +10,7 @@
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio_expander_21 4 GPIO_ACTIVE_HIGH>; /* ETH_PWR_EN */
off-on-delay = <500000>;
off-on-delay-us = <500000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_ETH";
@ -21,16 +19,106 @@
};
};
&backlight {
power-supply = <&reg_3p3v>;
};
/* Verdin SPI_1 */
&ecspi1 {
status = "okay";
};
/* EEPROM on display adapter boards */
&eeprom_display_adapter {
status = "okay";
};
/* EEPROM on Verdin Development board */
&eeprom_carrier_board {
status = "okay";
};
&eqos {
status = "okay";
};
&fec {
phy-supply = <&reg_eth2phy>;
status = "okay";
};
&flexcan1 {
status = "okay";
};
&flexcan2 {
status = "okay";
};
/* Verdin QSPI_1 */
&flexspi {
status = "okay";
};
&gpio_expander_21 {
status = "okay";
vcc-supply = <&reg_1p8v>;
};
/* Current measurement into module VCC */
&hwmon {
status = "okay";
};
&hwmon_temp {
vs-supply = <&reg_1p8v>;
status = "okay";
};
/* Verdin I2C_2_DSI */
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
/* Verdin I2C_1 */
&i2c4 {
status = "okay";
/* TODO: Audio Codec */
};
/* Verdin PCIE_1 */
&pcie {
status = "okay";
};
&pcie_phy {
status = "okay";
};
/* Verdin PWM_1 */
&pwm1 {
status = "okay";
};
/* Verdin PWM_2 */
&pwm2 {
status = "okay";
};
/* Verdin PWM_3_DSI */
&pwm3 {
status = "okay";
};
&reg_usdhc2_vmmc {
vin-supply = <&reg_3p3v>;
};
/* TODO: Verdin I2C_1 with Audio Codec */
/* Verdin UART_1, connector X50 through RS485 transceiver */
@ -38,9 +126,40 @@
linux,rs485-enabled-at-boot-time;
rs485-rts-active-low;
rs485-rx-during-tx;
status = "okay";
};
/* Verdin UART_2 */
&uart2 {
status = "okay";
};
/* Verdin UART_3, used as the Linux Console */
&uart3 {
status = "okay";
};
/* Verdin USB_1 */
&usb3_0 {
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
/* Verdin USB_2 */
&usb3_1 {
fsl,permanently-attached;
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
/* Limit frequency on dev board due to long traces and bad signal integrity */
&usdhc2 {
max-frequency = <100000000>;
status = "okay";
};

8
arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
View File

@ -62,6 +62,10 @@
&gpio4 {
bootph-pre-ram;
ctrl-sleep-moci-hog {
bootph-pre-ram;
};
};
&gpio5 {
@ -106,6 +110,10 @@
bootph-pre-ram;
};
&pinctrl_ctrl_sleep_moci {
bootph-pre-ram;
};
&pinctrl_i2c1 {
bootph-pre-ram;
};

5
arch/arm/dts/imx8mp-verdin-wifi.dtsi
View File

@ -65,6 +65,11 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt_uart>;
status = "okay";
bluetooth {
compatible = "mrvl,88w8997";
max-speed = <921600>;
};
};
/* On-module Wi-Fi */

91
arch/arm/dts/imx8mp-verdin.dtsi
View File

@ -3,7 +3,8 @@
* Copyright 2022 Toradex
*/
#include "dt-bindings/pwm/pwm.h"
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8mp.dtsi"
/ {
@ -49,7 +50,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
button-wakeup {
key-wakeup {
debounce-interval = <10>;
/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
@ -86,7 +87,7 @@
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
off-on-delay = <500000>;
off-on-delay-us = <500000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_eth>;
regulator-always-on;
@ -127,7 +128,7 @@
enable-active-high;
/* Verdin SD_1_PWR_EN (SODIMM 76) */
gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
off-on-delay = <100000>;
off-on-delay-us = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
regulator-max-microvolt = <3300000>;
@ -354,16 +355,6 @@
"SODIMM_82",
"SODIMM_70",
"SODIMM_72";
ctrl-sleep-moci-hog {
gpio-hog;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <29 GPIO_ACTIVE_HIGH>;
line-name = "CTRL_SLEEP_MOCI#";
output-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
};
&gpio3 {
@ -432,6 +423,16 @@
"SODIMM_256",
"SODIMM_48",
"SODIMM_44";
ctrl-sleep-moci-hog {
gpio-hog;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <29 GPIO_ACTIVE_HIGH>;
line-name = "CTRL_SLEEP_MOCI#";
output-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
};
/* On-module I2C */
@ -452,7 +453,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x25>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
/*
* The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the
@ -678,8 +678,8 @@
status = "disabled";
};
lvds_ti_sn65dsi83: bridge@2c {
compatible = "ti,sn65dsi83";
lvds_ti_sn65dsi84: bridge@2c {
compatible = "ti,sn65dsi84";
/* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
/* Verdin GPIO_10_DSI (SODIMM 21) */
enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
@ -712,7 +712,7 @@
compatible = "atmel,maxtouch";
/*
* Verdin GPIO_9_DSI
* (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
* (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
*/
interrupt-parent = <&gpio4>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
@ -748,7 +748,20 @@
};
};
/* TODO: Verdin PCIE_1 */
/* Verdin PCIE_1 */
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
/* PCIE_1_RESET# (SODIMM 244) */
reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
};
&pcie_phy {
clocks = <&hsio_blk_ctrl>;
clock-names = "ref";
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
};
/* Verdin PWM_1 */
&pwm1 {
@ -806,28 +819,45 @@
};
/* Verdin USB_1 */
&usb3_phy0 {
vbus-supply = <&reg_usb1_vbus>;
&usb3_0 {
fsl,disable-port-power-control;
fsl,over-current-active-low;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_1_oc_n>;
};
&usb_dwc3_0 {
/* dual role only, not full featured OTG */
adp-disable;
dr_mode = "otg";
hnp-disable;
maximum-speed = "high-speed";
over-current-active-low;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_1_id>;
role-switch-default-mode = "peripheral";
srp-disable;
usb-role-switch;
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
label = "Type-C";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_1_id>;
self-powered;
type = "micro";
vbus-supply = <&reg_usb1_vbus>;
};
};
/* Verdin USB_2 */
&usb3_1 {
fsl,disable-port-power-control;
};
&usb3_phy1 {
vbus-supply = <&reg_usb2_vbus>;
};
&usb_dwc3_1 {
disable-over-current;
dr_mode = "host";
};
@ -1045,7 +1075,6 @@
pinctrl_gpio_hog3: gpiohog3grp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1c4>, /* SODIMM 157 */
/* CSI_1_MCLK */
<MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */
};
@ -1220,7 +1249,7 @@
pinctrl_usb1_vbus: usb1vbusgrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x19>; /* SODIMM 155 */
<MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x106>; /* SODIMM 155 */
};
/* USB_1_ID */
@ -1229,9 +1258,15 @@
<MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */
};
/* USB_1_OC# */
pinctrl_usb_1_oc_n: usb1ocngrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c4>; /* SODIMM 157 */
};
pinctrl_usb2_vbus: usb2vbusgrp {
fsl,pins =
<MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19>; /* SODIMM 185 */
<MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x106>; /* SODIMM 185 */
};
/* On-module Wi-Fi */

502
arch/arm/dts/imx8mp.dtsi
View File

@ -123,6 +123,7 @@
A53_L2: l2-cache0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
@ -379,6 +380,8 @@
compatible = "fsl,imx8mp-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
nvmem-cells = <&tmu_calib>;
nvmem-cell-names = "calib";
#thermal-sensor-cells = <1>;
};
@ -406,12 +409,36 @@
status = "disabled";
};
gpt1: timer@302d0000 {
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
reg = <0x302d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>;
clock-names = "ipg", "per";
};
gpt2: timer@302e0000 {
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
reg = <0x302e0000 0x10000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>;
clock-names = "ipg", "per";
};
gpt3: timer@302f0000 {
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
reg = <0x302f0000 0x10000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>;
clock-names = "ipg", "per";
};
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx8mp-iomuxc";
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
gpr: syscon@30340000 {
compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
@ -424,27 +451,44 @@
#address-cells = <1>;
#size-cells = <1>;
imx8mp_uid: unique-id@420 {
/*
* The register address below maps to the MX8M
* Fusemap Description Table entries this way.
* Assuming
* reg = <ADDR SIZE>;
* then
* Fuse Address = (ADDR * 4) + 0x400
* Note that if SIZE is greater than 4, then
* each subsequent fuse is located at offset
* +0x10 in Fusemap Description Table (e.g.
* reg = <0x8 0x8> describes fuses 0x420 and
* 0x430).
*/
imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
reg = <0x8 0x8>;
};
cpu_speed_grade: speed-grade@10 {
cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
eth_mac1: mac-address@90 {
eth_mac1: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
eth_mac2: mac-address@96 {
eth_mac2: mac-address@96 { /* 0x658 */
reg = <0x96 6>;
};
tmu_calib: calib@264 { /* 0xd90-0xdc0 */
reg = <0x264 0x10>;
};
};
anatop: anatop@30360000 {
compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
"syscon";
anatop: clock-controller@30360000 {
compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
reg = <0x30360000 0x10000>;
#clock-cells = <1>;
};
snvs: snvs@30370000 {
@ -523,6 +567,7 @@
compatible = "fsl,imx8mp-gpc";
reg = <0x303a0000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
@ -589,7 +634,7 @@
reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
};
pgc_hsiomix: power-domains@17 {
pgc_hsiomix: power-domain@17 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
@ -631,6 +676,14 @@
reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
};
pgc_mlmix: power-domain@24 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
clocks = <&clk IMX8MP_CLK_ML_AXI>,
<&clk IMX8MP_CLK_ML_AHB>,
<&clk IMX8MP_CLK_NPU_ROOT>;
};
};
};
};
@ -693,6 +746,30 @@
clocks = <&osc_24m>;
clock-names = "per";
};
gpt6: timer@306e0000 {
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
reg = <0x306e0000 0x10000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>;
clock-names = "ipg", "per";
};
gpt5: timer@306f0000 {
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
reg = <0x306f0000 0x10000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>;
clock-names = "ipg", "per";
};
gpt4: timer@30700000 {
compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
reg = <0x30700000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>;
clock-names = "ipg", "per";
};
};
aips3: bus@30800000 {
@ -702,112 +779,129 @@
#size-cells = <1>;
ranges;
ecspi1: spi@30820000 {
spba-bus@30800000 {
compatible = "fsl,spba-bus", "simple-bus";
reg = <0x30800000 0x100000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
<&clk IMX8MP_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
#size-cells = <1>;
ranges;
ecspi2: spi@30830000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
<&clk IMX8MP_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi1: spi@30820000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
<&clk IMX8MP_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi3: spi@30840000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
<&clk IMX8MP_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi2: spi@30830000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
<&clk IMX8MP_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@30860000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30860000 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
<&clk IMX8MP_CLK_UART1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi3: spi@30840000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
<&clk IMX8MP_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
uart3: serial@30880000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30880000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
<&clk IMX8MP_CLK_UART3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@30860000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30860000 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
<&clk IMX8MP_CLK_UART1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart2: serial@30890000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30890000 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
<&clk IMX8MP_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart3: serial@30880000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30880000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
<&clk IMX8MP_CLK_UART3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
flexcan1: can@308c0000 {
compatible = "fsl,imx8mp-flexcan";
reg = <0x308c0000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_CAN1_ROOT>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
uart2: serial@30890000 {
compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
reg = <0x30890000 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
<&clk IMX8MP_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
flexcan2: can@308d0000 {
compatible = "fsl,imx8mp-flexcan";
reg = <0x308d0000 0x10000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_CAN2_ROOT>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
fsl,stop-mode = <&gpr 0x10 5>;
status = "disabled";
flexcan1: can@308c0000 {
compatible = "fsl,imx8mp-flexcan";
reg = <0x308c0000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_CAN1_ROOT>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
flexcan2: can@308d0000 {
compatible = "fsl,imx8mp-flexcan";
reg = <0x308d0000 0x10000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
<&clk IMX8MP_CLK_CAN2_ROOT>;
clock-names = "ipg", "per";
assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
assigned-clock-rates = <40000000>;
fsl,clk-source = /bits/ 8 <0>;
fsl,stop-mode = <&gpr 0x10 5>;
status = "disabled";
};
};
crypto: crypto@30900000 {
@ -1063,11 +1157,11 @@
noc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200M {
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
};
opp-1000M {
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
};
};
@ -1080,10 +1174,78 @@
#size-cells = <1>;
ranges;
mipi_dsi: dsi@32e60000 {
compatible = "fsl,imx8mp-mipi-dsim";
reg = <0x32e60000 0x400>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
clock-names = "bus_clk", "sclk_mipi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <200000000>, <24000000>;
samsung,pll-clock-frequency = <24000000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsim_from_lcdif1: endpoint {
remote-endpoint = <&lcdif1_to_dsim>;
};
};
};
};
lcdif1: display-controller@32e80000 {
compatible = "fsl,imx8mp-lcdif";
reg = <0x32e80000 0x10000>;
clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
status = "disabled";
port {
lcdif1_to_dsim: endpoint {
remote-endpoint = <&dsim_from_lcdif1>;
};
};
};
lcdif2: display-controller@32e90000 {
compatible = "fsl,imx8mp-lcdif";
reg = <0x32e90000 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
status = "disabled";
port {
lcdif2_to_ldb: endpoint {
remote-endpoint = <&ldb_from_lcdif2>;
};
};
};
media_blk_ctrl: blk-ctrl@32ec0000 {
compatible = "fsl,imx8mp-media-blk-ctrl",
"syscon";
reg = <0x32ec0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&pgc_mediamix>,
<&pgc_mipi_phy1>,
<&pgc_mipi_phy1>,
@ -1122,12 +1284,55 @@
"disp1", "disp2", "isp", "phy";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
<&clk IMX8MP_CLK_MEDIA_APB>;
<&clk IMX8MP_CLK_MEDIA_APB>,
<&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
<&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
<&clk IMX8MP_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_SYS_PLL1_800M>;
assigned-clock-rates = <500000000>, <200000000>;
<&clk IMX8MP_SYS_PLL1_800M>,
<&clk IMX8MP_VIDEO_PLL1_OUT>,
<&clk IMX8MP_VIDEO_PLL1_OUT>;
assigned-clock-rates = <500000000>, <200000000>,
<0>, <0>, <1039500000>;
#power-domain-cells = <1>;
lvds_bridge: bridge@5c {
compatible = "fsl,imx8mp-ldb";
reg = <0x5c 0x4>, <0x128 0x4>;
reg-names = "ldb", "lvds";
clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
clock-names = "ldb";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ldb_from_lcdif2: endpoint {
remote-endpoint = <&lcdif2_to_ldb>;
};
};
port@1 {
reg = <1>;
ldb_lvds_ch0: endpoint {
};
};
port@2 {
reg = <2>;
ldb_lvds_ch1: endpoint {
};
};
};
};
};
pcie_phy: pcie-phy@32f00000 {
@ -1158,6 +1363,7 @@
<&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
#power-domain-cells = <1>;
#clock-cells = <0>;
};
};
@ -1165,6 +1371,13 @@
compatible = "fsl,imx8mp-pcie";
reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
reg-names = "dbi", "config";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI>,
<&clk IMX8MP_CLK_PCIE_ROOT>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@ -1192,6 +1405,32 @@
status = "disabled";
};
pcie_ep: pcie-ep@33800000 {
compatible = "fsl,imx8mp-pcie-ep";
reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
reg-names = "dbi", "addr_space";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI>,
<&clk IMX8MP_CLK_PCIE_ROOT>;
clock-names = "pcie", "pcie_bus", "pcie_aux";
assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
num-lanes = <1>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
interrupt-names = "dma";
fsl,max-link-speed = <3>;
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "apps", "turnoff";
phys = <&pcie_phy>;
phy-names = "pcie-phy";
num-ib-windows = <4>;
num-ob-windows = <4>;
status = "disabled";
};
gpu3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;
@ -1223,6 +1462,28 @@
power-domains = <&pgc_gpu2d>;
};
vpu_g1: video-codec@38300000 {
compatible = "nxp,imx8mm-vpu-g1";
reg = <0x38300000 0x10000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
assigned-clock-rates = <600000000>;
power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
};
vpu_g2: video-codec@38310000 {
compatible = "nxp,imx8mq-vpu-g2";
reg = <0x38310000 0x10000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
assigned-clock-rates = <500000000>;
power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
};
vpumix_blk_ctrl: blk-ctrl@38330000 {
compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
reg = <0x38330000 0x100>;
@ -1234,6 +1495,9 @@
<&clk IMX8MP_CLK_VPU_G2_ROOT>,
<&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
clock-names = "g1", "g2", "vc8000e";
assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;
assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
assigned-clock-rates = <600000000>, <600000000>;
interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
<&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
<&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
@ -1279,7 +1543,7 @@
reg = <0x32f10100 0x8>,
<0x381f0000 0x20>;
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
@ -1292,9 +1556,9 @@
usb_dwc3_0: usb@38100000 {
compatible = "snps,dwc3";
reg = <0x38100000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>,
<&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>;
clock-names = "bus_early", "ref", "suspend";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy0>, <&usb3_phy0>;
@ -1321,7 +1585,7 @@
reg = <0x32f10108 0x8>,
<0x382f0000 0x20>;
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
@ -1334,9 +1598,9 @@
usb_dwc3_1: usb@38200000 {
compatible = "snps,dwc3";
reg = <0x38200000 0x10000>;
clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
clocks = <&clk IMX8MP_CLK_USB_ROOT>,
<&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
<&clk IMX8MP_CLK_USB_SUSP>;
clock-names = "bus_early", "ref", "suspend";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy1>, <&usb3_phy1>;

3
arch/arm/include/asm/arch-imx8m/imx-regs.h
View File

@ -13,7 +13,7 @@
#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
#define M4_BOOTROM_BASE_ADDR 0x007E0000
#define MCU_BOOTROM_BASE_ADDR 0x007E0000
#define GPIO1_BASE_ADDR 0X30200000
#define GPIO2_BASE_ADDR 0x30210000
@ -40,6 +40,7 @@
#define UART1_BASE_ADDR 0x30860000
#define UART3_BASE_ADDR 0x30880000
#define UART2_BASE_ADDR 0x30890000
#define CAAM_BASE_ADDR 0x30900000
#define I2C1_BASE_ADDR 0x30A20000
#define I2C2_BASE_ADDR 0x30A30000
#define I2C3_BASE_ADDR 0x30A40000

2
arch/arm/include/asm/arch-imx9/ccm_regs.h
View File

@ -12,7 +12,7 @@
#define ARM_A55_MTR_BUS_CLK_ROOT 1
#define ARM_A55_CLK_ROOT 2
#define M33_CLK_ROOT 3
#define SENTINEL_CLK_ROOT 4
#define ELE_CLK_ROOT 4
#define BUS_WAKEUP_CLK_ROOT 5
#define BUS_AON_CLK_ROOT 6
#define WAKEUP_AXI_CLK_ROOT 7

2
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -23,7 +23,7 @@
#define GPU_ARB_END_ADDR 0x01803FFF
#define APBH_DMA_ARB_BASE_ADDR 0x01804000
#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
#define M4_BOOTROM_BASE_ADDR 0x007F8000
#define MCU_BOOTROM_BASE_ADDR 0x007F8000
#elif !defined(CONFIG_MX6SLL)
#define CAAM_ARB_BASE_ADDR 0x00100000

2
arch/arm/include/asm/arch-mx7/imx-regs.h
View File

@ -18,7 +18,7 @@
#define GIC400_ARB_END_ADDR 0x31007FFF
#define APBH_DMA_ARB_BASE_ADDR 0x33000000
#define APBH_DMA_ARB_END_ADDR 0x33007FFF
#define M4_BOOTROM_BASE_ADDR 0x00180000
#define MCU_BOOTROM_BASE_ADDR 0x00180000
#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)

4
arch/arm/include/asm/global_data.h
View File

@ -92,8 +92,8 @@ struct arch_global_data {
struct udevice *scu_dev;
#endif
#ifdef CONFIG_IMX_SENTINEL
struct udevice *s400_dev;
#ifdef CONFIG_IMX_ELE
struct udevice *ele_dev;
u32 soc_rev;
u32 lifecycle;
u32 uid[4];

15
arch/arm/include/asm/mach-imx/ahab.h Normal file
View File

@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 NXP
*/
#ifndef __IMX_AHAB_H__
#define __IMX_AHAB_H__
#include <asm/mach-imx/image.h>
int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length);
int ahab_auth_release(void);
int ahab_verify_cntr_image(struct boot_img_t *img, int image_index);
#endif

53
arch/arm/include/asm/mach-imx/s400_api.h → arch/arm/include/asm/mach-imx/ele_api.h
View File

@ -3,12 +3,12 @@
* Copyright 2021 NXP
*/
#ifndef __S400_API_H__
#define __S400_API_H__
#ifndef __ELE_API_H__
#define __ELE_API_H__
#define AHAB_VERSION 0x6
#define AHAB_CMD_TAG 0x17
#define AHAB_RESP_TAG 0xe1
#define ELE_VERSION 0x6
#define ELE_CMD_TAG 0x17
#define ELE_RESP_TAG 0xe1
/* ELE commands */
#define ELE_PING_REQ (0x01)
@ -24,6 +24,8 @@
#define ELE_GET_FW_VERSION_REQ (0x9D)
#define ELE_RET_LIFECYCLE_UP_REQ (0xA0)
#define ELE_GET_EVENTS_REQ (0xA2)
#define ELE_START_RNG (0xA3)
#define ELE_GENERATE_DEK_BLOB (0xAF)
#define ELE_ENABLE_PATCH_REQ (0xC3)
#define ELE_RELEASE_RDC_REQ (0xC4)
#define ELE_GET_FW_STATUS_REQ (0xC5)
@ -109,17 +111,17 @@
#define ELE_SUCCESS_IND (0xD6)
#define ELE_FAILURE_IND (0x29)
#define S400_MAX_MSG 255U
#define ELE_MAX_MSG 255U
struct sentinel_msg {
struct ele_msg {
u8 version;
u8 size;
u8 command;
u8 tag;
u32 data[(S400_MAX_MSG - 1U)];
u32 data[(ELE_MAX_MSG - 1U)];
};
struct sentinel_get_info_data {
struct ele_get_info_data {
u32 hdr;
u32 soc;
u32 lc;
@ -130,19 +132,22 @@ struct sentinel_get_info_data {
u32 state;
};
int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ahab_release_container(u32 *response);
int ahab_verify_image(u32 img_id, u32 *response);
int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
int ahab_release_caam(u32 core_did, u32 *response);
int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
int ahab_get_fw_status(u32 *status, u32 *response);
int ahab_release_m33_trout(void);
int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response);
int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response);
int ele_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ele_release_container(u32 *response);
int ele_verify_image(u32 img_id, u32 *response);
int ele_forward_lifecycle(u16 life_cycle, u32 *response);
int ele_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
int ele_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
int ele_release_caam(u32 core_did, u32 *response);
int ele_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
int ele_get_events(u32 *events, u32 *events_cnt, u32 *response);
int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_output_size);
int ele_dump_buffer(u32 *buffer, u32 buffer_length);
int ele_get_info(struct ele_get_info_data *info, u32 *response);
int ele_get_fw_status(u32 *status, u32 *response);
int ele_release_m33_trout(void);
int ele_write_secure_fuse(ulong signed_msg_blk, u32 *response);
int ele_return_lifecycle_update(ulong signed_msg_blk, u32 *response);
int ele_start_rng(void);
#endif

1
arch/arm/include/asm/mach-imx/sys_proto.h
View File

@ -236,6 +236,7 @@ void board_mem_get_layout(u64 *phys_sdram_1_start,
u64 *phys_sdram_2_start,
u64 *phys_sdram_2_size);
int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data);
int arch_auxiliary_core_check_up(u32 core_id);
int board_mmc_get_env_dev(int devno);

9
arch/arm/mach-imx/Kconfig
View File

@ -31,7 +31,7 @@ config IMX_RDC
config IMX_BOOTAUX
bool "Support boot auxiliary core"
depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8M
depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8 || ARCH_IMX8M
help
bootaux [addr] to boot auxiliary core.
@ -86,6 +86,7 @@ config CMD_DEKBLOB
select IMX_CAAM_DEK_ENCAP if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP
select IMX_OPTEE_DEK_ENCAP if ARCH_IMX8M
select IMX_SECO_DEK_ENCAP if ARCH_IMX8
select IMX_ELE_DEK_ENCAP if ARCH_IMX8ULP || ARCH_IMX9
help
This enables the 'dek_blob' command which is used with the
Freescale secure boot mechanism. This command encapsulates and
@ -113,6 +114,12 @@ config IMX_SECO_DEK_ENCAP
This enabled the DEK blob encapsulation with the SECO API. This option
is only available on imx8.
config IMX_ELE_DEK_ENCAP
bool "Support the DEK blob encapsulation with ELE"
help
This enabled the DEK blob encapsulation with the ELE API. This option
is only available on imx8ulp and imx9.
config CMD_PRIBLOB
bool "Support the set_priblob_bitfield command"
depends on HAS_CAAM && IMX_HAB

5
arch/arm/mach-imx/Makefile
View File

@ -66,6 +66,11 @@ ifeq ($(SOC),$(filter $(SOC),vf610))
obj-y += ddrmc-vf610.o
obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o
endif
ifeq ($(SOC),$(filter $(SOC),imx8))
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
endif
endif
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o

89
arch/arm/mach-imx/cmd_dek.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008-2015 Freescale Semiconductor, Inc.
* Copyright 2022 NXP
*
* Command for encapsulating DEK blob
*/
@ -20,6 +21,11 @@
#include <firmware/imx/sci/sci.h>
#include <asm/mach-imx/image.h>
#endif
#ifdef CONFIG_IMX_ELE_DEK_ENCAP
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/image.h>
#endif
#include <cpu_func.h>
/**
@ -101,6 +107,7 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
0x0, &shm_output);
if (ret < 0) {
printf("Cannot register output shared memory 0x%X\n", ret);
tee_shm_free(shm_input);
goto error;
}
@ -122,11 +129,11 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
if (ret < 0)
printf("Cannot generate Blob with PTA DEK Blob 0x%X\n", ret);
error:
/* Free shared memory */
tee_shm_free(shm_input);
tee_shm_free(shm_output);
error:
/* Close session */
ret = tee_close_session(dev, arg.session);
if (ret < 0)
@ -154,7 +161,7 @@ error:
static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
{
sc_err_t err;
int err;
sc_rm_mr_t mr_input, mr_output;
struct generate_key_blob_hdr hdr;
u8 in_size, out_size;
@ -283,6 +290,84 @@ error:
}
#endif /* CONFIG_IMX_SECO_DEK_ENCAP */
#ifdef CONFIG_IMX_ELE_DEK_ENCAP
#define DEK_BLOB_HDR_SIZE 8
#define AHAB_PRIVATE_KEY 0x81
#define AHAB_DEK_BLOB 0x01
#define AHAB_ALG_AES 0x03
#define AHAB_128_AES_KEY 0x10
#define AHAB_192_AES_KEY 0x18
#define AHAB_256_AES_KEY 0x20
static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
{
u8 in_size, out_size;
u8 *src_ptr, *dst_ptr;
struct generate_key_blob_hdr hdr;
/* Set sizes */
in_size = sizeof(struct generate_key_blob_hdr) + len / 8;
out_size = BLOB_SIZE(len / 8) + DEK_BLOB_HDR_SIZE;
/* Get src and dst virtual addresses */
src_ptr = map_sysmem(src_addr, in_size);
dst_ptr = map_sysmem(dst_addr, out_size);
/* Check addr input */
if (!(src_ptr && dst_ptr)) {
debug("src_addr or dst_addr invalid\n");
return -1;
}
/* Build key header */
hdr.version = 0x0;
hdr.length_lsb = in_size;
hdr.length_msb = 0x00;
hdr.tag = AHAB_PRIVATE_KEY;
hdr.flags = AHAB_DEK_BLOB;
hdr.algorithm = AHAB_ALG_AES;
hdr.mode = 0x0; /* Not used by the ELE */
switch (len) {
case 128:
hdr.size = AHAB_128_AES_KEY;
break;
case 192:
hdr.size = AHAB_192_AES_KEY;
break;
case 256:
hdr.size = AHAB_256_AES_KEY;
break;
default:
/* Not supported */
debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n");
return -1;
}
/* Move input key and append blob header */
memmove((void *)(src_ptr + sizeof(struct generate_key_blob_hdr)),
(void *)src_ptr, len / 8);
memcpy((void *)src_ptr, (void *)&hdr,
sizeof(struct generate_key_blob_hdr));
/* Flush the cache */
flush_dcache_range(src_addr, src_addr + in_size);
flush_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr +
roundup(out_size, ARCH_DMA_MINALIGN)));
/* Call ELE */
if (ele_generate_dek_blob(0x00, src_addr, dst_addr, out_size))
return -1;
/* Invalidate output buffer */
invalidate_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr +
roundup(out_size, ARCH_DMA_MINALIGN)));
return 0;
}
#endif /* CONFIG_IMX_ELE_DEK_ENCAP */
/**
* do_dek_blob() - Handle the "dek_blob" command-line command
* @cmdtp: Command data struct pointer

91
arch/arm/mach-imx/ele_ahab.c
View File

@ -7,14 +7,13 @@
#include <command.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/mach-imx/s400_api.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/image.h>
#include <console.h>
#include <cpu_func.h>
#include <asm/mach-imx/ahab.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
@ -267,7 +266,7 @@ int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
flush_dcache_range(IMG_CONTAINER_BASE,
IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1);
err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp);
err = ele_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp);
if (err) {
printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
err, resp);
@ -282,7 +281,7 @@ int ahab_auth_release(void)
int err;
u32 resp;
err = ahab_release_container(&resp);
err = ele_release_container(&resp);
if (err) {
printf("Error: release container failed, resp 0x%x!\n", resp);
display_ahab_auth_ind(resp);
@ -296,7 +295,7 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
int err;
u32 resp;
err = ahab_verify_image(image_index, &resp);
err = ele_verify_image(image_index, &resp);
if (err) {
printf("Authenticate img %d failed, return %d, resp 0x%x\n",
image_index, err, resp);
@ -403,7 +402,7 @@ static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc,
if (argc < 2)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[1], NULL, 16);
addr = hextoul(argv[1], NULL);
printf("Authenticate OS container at 0x%lx\n", addr);
@ -485,7 +484,7 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
return -EPERM;
}
err = ahab_forward_lifecycle(8, &resp);
err = ele_forward_lifecycle(8, &resp);
if (err != 0) {
printf("Error in forward lifecycle to OEM closed\n");
return -EIO;
@ -502,7 +501,7 @@ int ahab_dump(void)
int ret, i = 0;
do {
ret = ahab_dump_buffer(buffer, 32);
ret = ele_dump_buffer(buffer, 32);
if (ret < 0) {
printf("Error in dump AHAB log\n");
return -EIO;
@ -547,7 +546,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const
display_life_cycle(lc);
ret = ahab_get_events(events, &cnt, NULL);
ret = ele_get_events(events, &cnt, NULL);
if (ret) {
printf("Get ELE EVENTS error %d\n", ret);
return CMD_RET_FAILURE;
@ -564,6 +563,68 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const
return 0;
}
static int do_sec_fuse_prog(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
ulong addr;
u32 header, response;
if (argc < 2)
return CMD_RET_USAGE;
addr = hextoul(argv[1], NULL);
header = *(u32 *)addr;
if ((header & 0xff0000ff) != 0x89000000) {
printf("Wrong Signed message block format, header 0x%x\n", header);
return CMD_RET_FAILURE;
}
header = (header & 0xffff00) >> 8;
printf("Signed Message block at 0x%lx, size 0x%x\n", addr, header);
flush_dcache_range(addr, addr + header - 1);
if (ele_write_secure_fuse(addr, &response)) {
printf("Program secure fuse failed, response 0x%x\n", response);
return CMD_RET_FAILURE;
}
printf("Program secure fuse completed, response 0x%x\n", response);
return CMD_RET_SUCCESS;
}
static int do_ahab_return_lifecycle(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
ulong addr;
u32 header, response;
if (argc < 2)
return CMD_RET_USAGE;
addr = hextoul(argv[1], NULL);
header = *(u32 *)addr;
if ((header & 0xff0000ff) != 0x89000000) {
printf("Wrong Signed message block format, header 0x%x\n", header);
return CMD_RET_FAILURE;
}
header = (header & 0xffff00) >> 8;
printf("Signed Message block at 0x%lx, size 0x%x\n", addr, header);
flush_dcache_range(addr, addr + header - 1);
if (ele_return_lifecycle_update(addr, &response)) {
printf("Return lifecycle failed, response 0x%x\n", response);
return CMD_RET_FAILURE;
}
printf("Return lifecycle completed, response 0x%x\n", response);
return CMD_RET_SUCCESS;
}
U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
"autenticate OS container via AHAB",
"addr\n"
@ -584,3 +645,15 @@ U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status,
"display AHAB lifecycle only",
""
);
U_BOOT_CMD(ahab_sec_fuse_prog, CONFIG_SYS_MAXARGS, 1, do_sec_fuse_prog,
"Program secure fuse via signed message block",
"addr\n"
"addr - Signed message block for secure fuse\n"
);
U_BOOT_CMD(ahab_return_lifecycle, CONFIG_SYS_MAXARGS, 1, do_ahab_return_lifecycle,
"Return lifecycle to OEM field return via signed message block",
"addr\n"
"addr - Return lifecycle message block signed by OEM SRK\n"
);

41
arch/arm/mach-imx/hab.c
View File

@ -289,9 +289,10 @@ static char *rsn_str[] = {
};
static char *sts_str[] = {
"STS = HAB_SUCCESS (0xF0)\n",
"STS = HAB_STS_ANY (0x00)\n",
"STS = HAB_FAILURE (0x33)\n",
"STS = HAB_WARNING (0x69)\n",
"STS = HAB_SUCCESS (0xF0)\n",
"STS = INVALID\n",
NULL
};
@ -336,8 +337,7 @@ static uint8_t hab_statuses[5] = {
HAB_STS_ANY,
HAB_FAILURE,
HAB_WARNING,
HAB_SUCCESS,
-1
HAB_SUCCESS
};
static uint8_t hab_reasons[26] = {
@ -365,8 +365,7 @@ static uint8_t hab_reasons[26] = {
HAB_UNS_ITEM,
HAB_UNS_KEY,
HAB_UNS_PROTOCOL,
HAB_UNS_STATE,
-1
HAB_UNS_STATE
};
static uint8_t hab_contexts[12] = {
@ -380,8 +379,7 @@ static uint8_t hab_contexts[12] = {
HAB_CTX_COMMAND,
HAB_CTX_AUT_DAT,
HAB_CTX_ASSERT,
HAB_CTX_EXIT,
-1
HAB_CTX_EXIT
};
static uint8_t hab_engines[16] = {
@ -399,30 +397,35 @@ static uint8_t hab_engines[16] = {
HAB_ENG_ROM,
HAB_ENG_HDCP,
HAB_ENG_RTL,
HAB_ENG_SW,
-1
HAB_ENG_SW
};
static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
static inline u32 get_idx(u8 *list, u8 tgt, u32 size)
{
uint8_t idx = 0;
uint8_t element = list[idx];
while (element != -1) {
u32 idx = 0;
u8 element;
while (idx < size) {
element = list[idx];
if (element == tgt)
return idx;
element = list[++idx];
++idx;
}
return -1;
return idx;
}
static void process_event_record(uint8_t *event_data, size_t bytes)
{
struct record *rec = (struct record *)event_data;
printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0],
ARRAY_SIZE(hab_statuses))]);
printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1],
ARRAY_SIZE(hab_reasons))]);
printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2],
ARRAY_SIZE(hab_contexts))]);
printf("%s", eng_str[get_idx(hab_engines, rec->contents[3],
ARRAY_SIZE(hab_engines))]);
}
static void display_event(uint8_t *event_data, size_t bytes)

96
arch/arm/mach-imx/image-container.c
View File

@ -22,6 +22,25 @@
#define QSPI_NOR_DEV 3
#define ROM_API_DEV 4
/* The unit of second image offset number which provision by the fuse bits */
#define SND_IMG_OFF_UNIT (0x100000UL)
/*
* If num = 0, off = (2 ^ 2) * 1MB
* else If num = 2, off = (2 ^ 0) * 1MB
* else off = (2 ^ num) * 1MB
*/
#define SND_IMG_NUM_TO_OFF(num) \
((1UL << ((0 == (num)) ? 2 : (2 == (num)) ? 0 : (num))) * SND_IMG_OFF_UNIT)
#define GET_SND_IMG_NUM(fuse) (((fuse) >> 24) & 0x1F)
#if defined(CONFIG_IMX8QM)
#define FUSE_IMG_SET_OFF_WORD 464
#elif defined(CONFIG_IMX8QXP)
#define FUSE_IMG_SET_OFF_WORD 720
#endif
int get_container_size(ulong addr, u16 *header_length)
{
struct container_hdr *phdr;
@ -31,7 +50,7 @@ int get_container_size(ulong addr, u16 *header_length)
u32 max_offset = 0, img_end;
phdr = (struct container_hdr *)addr;
if (phdr->tag != 0x87 && phdr->version != 0x0) {
if (phdr->tag != 0x87 || phdr->version != 0x0) {
debug("Wrong container header\n");
return -EFAULT;
}
@ -136,15 +155,53 @@ static int get_dev_container_size(void *dev, int dev_type, unsigned long offset,
return ret;
}
static bool check_secondary_cnt_set(unsigned long *set_off)
{
#if IS_ENABLED(CONFIG_ARCH_IMX8)
int ret;
u8 set_id = 1;
u32 fuse_val = 0;
if (!(is_imx8qxp() && is_soc_rev(CHIP_REV_B))) {
ret = sc_misc_get_boot_container(-1, &set_id);
if (ret)
return false;
/* Secondary boot */
if (set_id == 2) {
ret = sc_misc_otp_fuse_read(-1, FUSE_IMG_SET_OFF_WORD, &fuse_val);
if (!ret) {
if (set_off)
*set_off = SND_IMG_NUM_TO_OFF(GET_SND_IMG_NUM(fuse_val));
return true;
}
}
}
#endif
return false;
}
static unsigned long get_boot_device_offset(void *dev, int dev_type)
{
unsigned long offset = 0;
unsigned long offset = 0, sec_set_off = 0;
bool sec_boot = false;
if (dev_type == ROM_API_DEV) {
offset = (unsigned long)dev;
return offset;
}
sec_boot = check_secondary_cnt_set(&sec_set_off);
if (sec_boot)
printf("Secondary set selected\n");
else
printf("Primary set selected\n");
if (dev_type == MMC_DEV) {
struct mmc *mmc = (struct mmc *)dev;
if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) {
offset = CONTAINER_HDR_MMCSD_OFFSET;
offset = sec_boot ? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET;
} else {
u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
@ -154,19 +211,23 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type)
else
offset = CONTAINER_HDR_EMMC_OFFSET;
} else {
offset = CONTAINER_HDR_MMCSD_OFFSET;
offset = sec_boot ? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET;
}
}
} else if (dev_type == QSPI_DEV) {
offset = CONTAINER_HDR_QSPI_OFFSET;
offset = sec_boot ? (sec_set_off + CONTAINER_HDR_QSPI_OFFSET) :
CONTAINER_HDR_QSPI_OFFSET;
} else if (dev_type == NAND_DEV) {
offset = CONTAINER_HDR_NAND_OFFSET;
offset = sec_boot ? (sec_set_off + CONTAINER_HDR_NAND_OFFSET) :
CONTAINER_HDR_NAND_OFFSET;
} else if (dev_type == QSPI_NOR_DEV) {
offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000;
} else if (dev_type == ROM_API_DEV) {
offset = (unsigned long)dev;
} else {
printf("Not supported dev_type: %d\n", dev_type);
}
debug("container set offset 0x%lx\n", offset);
return offset;
}
@ -227,6 +288,25 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
return end / mmc->read_bl_len;
}
int spl_mmc_emmc_boot_partition(struct mmc *mmc)
{
int part;
part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
if (part == 1 || part == 2) {
unsigned long sec_set_off = 0;
bool sec_boot = false;
sec_boot = check_secondary_cnt_set(&sec_set_off);
if (sec_boot)
part = (part == 1) ? 2 : 1;
} else if (part == 7) {
part = 0;
}
return part;
}
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT

161
arch/arm/mach-imx/imx8/ahab.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Copyright 2018-2019, 2022 NXP
*/
#include <common.h>
@ -16,6 +16,8 @@
#include <asm/mach-imx/image.h>
#include <console.h>
#include <cpu_func.h>
#include "u-boot/sha256.h"
#include <asm/mach-imx/ahab.h>
DECLARE_GLOBAL_DATA_PTR;
@ -24,6 +26,86 @@ DECLARE_GLOBAL_DATA_PTR;
#define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE (0x60000000UL)
#define SECO_PT 2U
#define AHAB_HASH_TYPE_MASK 0x00000700
#define AHAB_HASH_TYPE_SHA256 0
int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
{
int err;
memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container,
ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
if (err)
printf("Authenticate container hdr failed, return %d\n", err);
return err;
}
int ahab_auth_release(void)
{
int err;
err = sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0);
if (err)
printf("Error: release container failed!\n");
return err;
}
int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
{
sc_faddr_t start, end;
sc_rm_mr_t mr;
int err;
int ret = 0;
debug("img %d, dst 0x%llx, src 0x%x, size 0x%x\n",
image_index, img->dst, img->offset, img->size);
/* Find the memreg and set permission for seco pt */
err = sc_rm_find_memreg(-1, &mr,
img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1);
if (err) {
printf("Error: can't find memreg for image load address 0x%llx, error %d\n",
img->dst, err);
return -ENOMEM;
}
err = sc_rm_get_memreg_info(-1, mr, &start, &end);
if (!err)
debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
err = sc_rm_set_memreg_permissions(-1, mr,
SECO_PT, SC_RM_PERM_FULL);
if (err) {
printf("Set permission failed for img %d, error %d\n",
image_index, err);
return -EPERM;
}
err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
1 << image_index);
if (err) {
printf("Authenticate img %d failed, return %d\n",
image_index, err);
ret = -EIO;
}
err = sc_rm_set_memreg_permissions(-1, mr,
SECO_PT, SC_RM_PERM_NONE);
if (err) {
printf("Remove permission failed for img %d, error %d\n",
image_index, err);
ret = -EPERM;
}
return ret;
}
static inline bool check_in_dram(ulong addr)
{
@ -46,11 +128,12 @@ int authenticate_os_container(ulong addr)
struct container_hdr *phdr;
int i, ret = 0;
int err;
sc_rm_mr_t mr;
sc_faddr_t start, end;
u16 length;
struct boot_img_t *img;
unsigned long s, e;
#ifdef CONFIG_ARMV8_CE_SHA256
u8 hash_value[SHA256_SUM_LEN];
#endif
if (addr % 4) {
puts("Error: Image's address is not 4 byte aligned\n");
@ -76,14 +159,9 @@ int authenticate_os_container(ulong addr)
length = phdr->length_lsb + (phdr->length_msb << 8);
debug("container length %u\n", length);
memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)addr,
ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
err = ahab_auth_cntr_hdr(phdr, length);
if (err) {
printf("Authenticate container hdr failed, return %d\n",
err);
ret = -EIO;
goto exit;
}
@ -105,50 +183,27 @@ int authenticate_os_container(ulong addr)
flush_dcache_range(s, e);
/* Find the memreg and set permission for seco pt */
err = sc_rm_find_memreg(-1, &mr, s, e);
if (err) {
printf("Error: can't find memreg for image load address 0x%llx, error %d\n", img->dst, err);
ret = -ENOMEM;
goto exit;
#ifdef CONFIG_ARMV8_CE_SHA256
if (((img->hab_flags & AHAB_HASH_TYPE_MASK) >> 8) == AHAB_HASH_TYPE_SHA256) {
sha256_csum_wd((void *)img->dst, img->size, hash_value, CHUNKSZ_SHA256);
err = memcmp(&img->hash, &hash_value, SHA256_SUM_LEN);
if (err) {
printf("img %d hash comparison failed, error %d\n", i, err);
ret = -EIO;
goto exit;
}
} else {
#endif
ret = ahab_verify_cntr_image(img, i);
if (ret)
goto exit;
#ifdef CONFIG_ARMV8_CE_SHA256
}
err = sc_rm_get_memreg_info(-1, mr, &start, &end);
if (!err)
debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT,
SC_RM_PERM_FULL);
if (err) {
printf("Set permission failed for img %d, error %d\n",
i, err);
ret = -EPERM;
goto exit;
}
err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
(1 << i));
if (err) {
printf("Authenticate img %d failed, return %d\n",
i, err);
ret = -EIO;
}
err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT,
SC_RM_PERM_NONE);
if (err) {
printf("Remove permission failed for img %d, err %d\n",
i, err);
ret = -EPERM;
}
if (ret)
goto exit;
#endif
}
exit:
if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0) != SC_ERR_NONE)
printf("Error: release container failed!\n");
ahab_auth_release();
return ret;
}
@ -263,7 +318,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc,
u16 lc;
err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
if (err != SC_ERR_NONE) {
if (err) {
printf("Error in get lifecycle\n");
return -EIO;
}
@ -271,7 +326,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc,
display_life_cycle(lc);
err = sc_seco_get_event(-1, idx, &event);
while (err == SC_ERR_NONE) {
while (!err) {
printf("SECO Event[%u] = 0x%08X\n", idx, event);
display_ahab_auth_event(event);
@ -312,7 +367,7 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
return -EACCES;
err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
if (err != SC_ERR_NONE) {
if (err) {
printf("Error in get lifecycle\n");
return -EIO;
}
@ -324,7 +379,7 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
}
err = sc_seco_forward_lifecycle(-1, 16);
if (err != SC_ERR_NONE) {
if (err) {
printf("Error in forward lifecycle to OEM closed\n");
return -EIO;
}

180
arch/arm/mach-imx/imx8/cpu.c
View File

@ -26,6 +26,8 @@
#include <asm/armv8/mmu.h>
#include <asm/setup.h>
#include <asm/mach-imx/boot_mode.h>
#include <power-domain.h>
#include <elf.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
@ -107,6 +109,178 @@ int arch_misc_init(void)
}
#endif
#ifdef CONFIG_IMX_BOOTAUX
#ifdef CONFIG_IMX8QM
int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
{
sc_rsrc_t core_rsrc, mu_rsrc;
sc_faddr_t tcml_addr;
u32 tcml_size = SZ_128K;
ulong addr;
switch (core_id) {
case 0:
core_rsrc = SC_R_M4_0_PID0;
tcml_addr = 0x34FE0000;
mu_rsrc = SC_R_M4_0_MU_1A;
break;
case 1:
core_rsrc = SC_R_M4_1_PID0;
tcml_addr = 0x38FE0000;
mu_rsrc = SC_R_M4_1_MU_1A;
break;
default:
printf("Not support this core boot up, ID:%u\n", core_id);
return -EINVAL;
}
addr = (sc_faddr_t)boot_private_data;
if (addr >= tcml_addr && addr <= tcml_addr + tcml_size) {
printf("Wrong image address 0x%lx, should not in TCML\n",
addr);
return -EINVAL;
}
printf("Power on M4 and MU\n");
if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
return -EIO;
if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
return -EIO;
printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr);
if (addr != tcml_addr)
memcpy((void *)tcml_addr, (void *)addr, tcml_size);
printf("Start M4 %u\n", core_id);
if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE)
return -EIO;
printf("bootaux complete\n");
return 0;
}
#endif
#ifdef CONFIG_IMX8QXP
int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
{
sc_rsrc_t core_rsrc, mu_rsrc = SC_R_NONE;
sc_faddr_t aux_core_ram;
u32 size;
ulong addr;
switch (core_id) {
case 0:
core_rsrc = SC_R_M4_0_PID0;
aux_core_ram = 0x34FE0000;
mu_rsrc = SC_R_M4_0_MU_1A;
size = SZ_128K;
break;
case 1:
core_rsrc = SC_R_DSP;
aux_core_ram = 0x596f8000;
size = SZ_2K;
break;
default:
printf("Not support this core boot up, ID:%u\n", core_id);
return -EINVAL;
}
addr = (sc_faddr_t)boot_private_data;
if (addr >= aux_core_ram && addr <= aux_core_ram + size) {
printf("Wrong image address 0x%lx, should not in aux core ram\n",
addr);
return -EINVAL;
}
printf("Power on aux core %d\n", core_id);
if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
return -EIO;
if (mu_rsrc != SC_R_NONE) {
if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
return -EIO;
}
if (core_id == 1) {
struct power_domain pd;
if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) {
printf("Error enable clock\n");
return -EIO;
}
if (!power_domain_lookup_name("audio_sai0", &pd)) {
if (power_domain_on(&pd)) {
printf("Error power on SAI0\n");
return -EIO;
}
}
if (!power_domain_lookup_name("audio_ocram", &pd)) {
if (power_domain_on(&pd)) {
printf("Error power on HIFI RAM\n");
return -EIO;
}
}
}
printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram);
if (core_id == 0) {
/* M4 use bin file */
memcpy((void *)aux_core_ram, (void *)addr, size);
} else {
/* HIFI use elf file */
if (!valid_elf_image(addr))
return -1;
addr = load_elf_image_shdr(addr);
}
printf("Start %s\n", core_id == 0 ? "M4" : "HIFI");
if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE)
return -EIO;
printf("bootaux complete\n");
return 0;
}
#endif
int arch_auxiliary_core_check_up(u32 core_id)
{
sc_rsrc_t core_rsrc;
sc_pm_power_mode_t power_mode;
switch (core_id) {
case 0:
core_rsrc = SC_R_M4_0_PID0;
break;
#ifdef CONFIG_IMX8QM
case 1:
core_rsrc = SC_R_M4_1_PID0;
break;
#endif
default:
printf("Not support this core, ID:%u\n", core_id);
return 0;
}
if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE)
return 0;
if (power_mode != SC_PM_PW_MODE_OFF)
return 1;
return 0;
}
#endif
int print_bootinfo(void)
{
enum boot_device bt_dev = get_boot_device();
@ -195,7 +369,7 @@ enum boot_device get_boot_device(void)
#define FUSE_UNIQUE_ID_WORD1 17
void get_board_serial(struct tag_serialnr *serialnr)
{
sc_err_t err;
int err;
u32 val1 = 0, val2 = 0;
u32 word1, word2;
@ -206,13 +380,13 @@ void get_board_serial(struct tag_serialnr *serialnr)
word2 = FUSE_UNIQUE_ID_WORD1;
err = sc_misc_otp_fuse_read(-1, word1, &val1);
if (err != SC_ERR_NONE) {
if (err) {
printf("%s fuse %d read error: %d\n", __func__, word1, err);
return;
}
err = sc_misc_otp_fuse_read(-1, word2, &val2);
if (err != SC_ERR_NONE) {
if (err) {
printf("%s fuse %d read error: %d\n", __func__, word2, err);
return;
}

2
arch/arm/mach-imx/imx8/fdt.c
View File

@ -110,7 +110,7 @@ static int config_smmu_resource_sid(int rsrc, int sid)
err = sc_rm_set_master_sid(-1, rsrc, sid);
debug("set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err);
if (err != SC_ERR_NONE) {
if (err) {
if (!check_owned_resource(rsrc)) {
printf("%s rsrc[%d] not owned\n", __func__, rsrc);
return -1;

175
arch/arm/mach-imx/imx8/snvs_security_sc.c
View File

@ -286,16 +286,15 @@ static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2,
u32 *_p3, u32 *_p4, u32 *_p5,
u32 _cnt)
{
int scierr = 0;
int err;
u32 d1 = ptr_value(_p1);
u32 d2 = ptr_value(_p2);
u32 d3 = ptr_value(_p3);
u32 d4 = ptr_value(_p4);
u32 d5 = ptr_value(_p5);
scierr = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3,
&d4, &d4, _cnt);
if (scierr != SC_ERR_NONE) {
err = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3, &d4, &d4, _cnt);
if (err) {
printf("Failed to set secvio configuration\n");
debug("Failed to set conf id 0x%x with values ", id);
debug("0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x (cnt: %d)\n",
@ -315,7 +314,7 @@ static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2,
*(u32 *)_p5 = d5;
exit:
return scierr;
return err;
}
#define SC_CHECK_WRITE1(id, _p1) \
@ -323,7 +322,7 @@ exit:
static int apply_snvs_config(struct snvs_security_sc_conf *cnf)
{
int scierr = 0;
int err = 0;
debug("%s\n", __func__);
@ -365,92 +364,88 @@ static int apply_snvs_config(struct snvs_security_sc_conf *cnf)
cnf->lp.act_tamper_routing_ctl1,
cnf->lp.act_tamper_routing_ctl2);
scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg),
&cnf->lp.tamper_filt_cfg,
&cnf->lp.tamper_filt1_cfg,
&cnf->lp.tamper_filt2_cfg, NULL,
NULL, 3);
if (scierr != SC_ERR_NONE)
err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg),
&cnf->lp.tamper_filt_cfg,
&cnf->lp.tamper_filt1_cfg,
&cnf->lp.tamper_filt2_cfg,
NULL, NULL, 3);
if (err)
goto exit;
/* Configure AT */
scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg),
&cnf->lp.act_tamper1_cfg,
&cnf->lp.act_tamper2_cfg,
&cnf->lp.act_tamper2_cfg,
&cnf->lp.act_tamper2_cfg,
&cnf->lp.act_tamper2_cfg, 5);
if (scierr != SC_ERR_NONE)
err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg),
&cnf->lp.act_tamper1_cfg,
&cnf->lp.act_tamper2_cfg,
&cnf->lp.act_tamper2_cfg,
&cnf->lp.act_tamper2_cfg,
&cnf->lp.act_tamper2_cfg, 5);
if (err)
goto exit;
/* Configure AT routing */
scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1),
&cnf->lp.act_tamper_routing_ctl1,
&cnf->lp.act_tamper_routing_ctl2,
NULL, NULL, NULL, 2);
if (scierr != SC_ERR_NONE)
err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1),
&cnf->lp.act_tamper_routing_ctl1,
&cnf->lp.act_tamper_routing_ctl2,
NULL, NULL, NULL, 2);
if (err)
goto exit;
/* Configure AT frequency */
scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl),
&cnf->lp.act_tamper_clk_ctl);
if (scierr != SC_ERR_NONE)
err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl),
&cnf->lp.act_tamper_clk_ctl);
if (err)
goto exit;
/* Activate the ATs */
scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl),
&cnf->lp.act_tamper_ctl);
if (scierr != SC_ERR_NONE)
err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl), &cnf->lp.act_tamper_ctl);
if (err)
goto exit;
/* Activate the detectors */
scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg),
&cnf->lp.tamper_det_cfg,
&cnf->lp.tamper_det_cfg2, NULL, NULL,
NULL, 2);
if (scierr != SC_ERR_NONE)
err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg),
&cnf->lp.tamper_det_cfg,
&cnf->lp.tamper_det_cfg2, NULL, NULL, NULL, 2);
if (err)
goto exit;
/* Configure LP secvio */
scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl),
&cnf->lp.secvio_ctl);
if (scierr != SC_ERR_NONE)
err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl), &cnf->lp.secvio_ctl);
if (err)
goto exit;
/* Configure HP secvio */
scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl),
&cnf->hp.secvio_ctl);
if (scierr != SC_ERR_NONE)
err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl), &cnf->hp.secvio_ctl);
if (err)
goto exit;
/* Lock access */
scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock);
if (scierr != SC_ERR_NONE)
err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock);
if (err)
goto exit;
scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock);
if (scierr != SC_ERR_NONE)
err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock);
if (err)
goto exit;
exit:
return (scierr == SC_ERR_NONE) ? 0 : -EIO;
return err;
}
static int dgo_write(u32 _id, u8 _access, u32 *_pdata)
{
int scierr = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata);
int err = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata);
if (scierr != SC_ERR_NONE) {
if (err) {
printf("Failed to set dgo configuration\n");
debug("Failed to set conf id 0x%x : 0x%.8x", _id, *_pdata);
}
return scierr;
return err;
}
static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf)
{
int scierr = 0;
int err;
debug("%s\n", __func__);
@ -468,50 +463,50 @@ static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf)
cnf->tamper_misc_ctl,
cnf->tamper_core_volt_mon_ctl);
dgo_write(0x04, 1, &cnf->tamper_offset_ctl);
if (scierr != SC_ERR_NONE)
err = dgo_write(0x04, 1, &cnf->tamper_offset_ctl);
if (err)
goto exit;
dgo_write(0x14, 1, &cnf->tamper_pull_ctl);
if (scierr != SC_ERR_NONE)
err = dgo_write(0x14, 1, &cnf->tamper_pull_ctl);
if (err)
goto exit;
dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl);
if (scierr != SC_ERR_NONE)
err = dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl);
if (err)
goto exit;
dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl);
if (scierr != SC_ERR_NONE)
err = dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl);
if (err)
goto exit;
dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl);
if (scierr != SC_ERR_NONE)
err = dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl);
if (err)
goto exit;
/* Last as it could lock the writes */
dgo_write(0x44, 1, &cnf->tamper_misc_ctl);
if (scierr != SC_ERR_NONE)
err = dgo_write(0x44, 1, &cnf->tamper_misc_ctl);
if (err)
goto exit;
exit:
return (scierr == SC_ERR_NONE) ? 0 : -EIO;
return err;
}
static int pad_write(u32 _pad, u32 _value)
{
int scierr = sc_pad_set(-1, _pad, _value);
int err = sc_pad_set(-1, _pad, _value);
if (scierr != SC_ERR_NONE) {
if (err) {
printf("Failed to set pad configuration\n");
debug("Failed to set conf pad 0x%x : 0x%.8x", _pad, _value);
}
return scierr;
return err;
}
static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size)
{
int scierr = 0;
int err = 0;
u32 idx;
debug("%s\n", __func__);
@ -519,13 +514,13 @@ static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size)
for (idx = 0; idx < size; idx++) {
debug("\t idx %d: pad %d: 0x%.8x\n", idx, confs[idx].pad,
confs[idx].mux_conf);
pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf);
if (scierr != SC_ERR_NONE)
err = pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf);
if (err)
goto exit;
}
exit:
return (scierr == SC_ERR_NONE) ? 0 : -EIO;
return err;
}
int examples(void)
@ -753,7 +748,7 @@ static char snvs_clear_status_help_text[] =
static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
int scierr = 0;
int err;
u32 idx = 0;
struct snvs_security_sc_conf conf = {0};
@ -764,20 +759,18 @@ static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc,
conf.lp.status = hextoul(argv[++idx], NULL);
conf.lp.tamper_det_status = hextoul(argv[++idx], NULL);
scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status),
&conf.lp.status, NULL, NULL, NULL,
NULL, 1);
if (scierr != SC_ERR_NONE)
err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status),
&conf.lp.status, NULL, NULL, NULL, NULL, 1);
if (err)
goto exit;
scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status),
&conf.lp.tamper_det_status, NULL,
NULL, NULL, NULL, 1);
if (scierr != SC_ERR_NONE)
err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status),
&conf.lp.tamper_det_status, NULL, NULL, NULL, NULL, 1);
if (err)
goto exit;
exit:
return (scierr == SC_ERR_NONE) ? 0 : 1;
return err;
}
U_BOOT_CMD(snvs_clear_status,
@ -793,7 +786,7 @@ static char snvs_sec_status_help_text[] =
static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
int scierr;
int err;
u32 idx;
u32 data[5];
@ -864,8 +857,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
for (idx = 0; idx < ARRAY_SIZE(pads); idx++) {
u8 pad_id = pads[idx];
scierr = sc_pad_get(-1, pad_id, &data[0]);
if (scierr == 0)
err = sc_pad_get(-1, pad_id, &data[0]);
if (!err)
printf("\t- Pin %d: %.8x\n", pad_id, data[0]);
else
printf("Failed to read Pin %d\n", pad_id);
@ -876,8 +869,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
for (idx = 0; idx < ARRAY_SIZE(fuses); idx++) {
u32 fuse_id = fuses[idx];
scierr = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]);
if (scierr == 0)
err = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]);
if (!err)
printf("\t- Fuse %d: %.8x\n", fuse_id, data[0]);
else
printf("Failed to read Fuse %d\n", fuse_id);
@ -888,10 +881,10 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
for (idx = 0; idx < ARRAY_SIZE(snvs); idx++) {
struct snvs_reg *reg = &snvs[idx];
scierr = sc_seco_secvio_config(-1, reg->id, 0, &data[0],
&data[1], &data[2], &data[3],
&data[4], reg->nb);
if (scierr == 0) {
err = sc_seco_secvio_config(-1, reg->id, 0, &data[0],
&data[1], &data[2], &data[3],
&data[4], reg->nb);
if (!err) {
int subidx;
printf("\t- SNVS %.2x(%d):", reg->id, reg->nb);
@ -908,8 +901,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
for (idx = 0; idx < ARRAY_SIZE(dgo); idx++) {
u8 dgo_id = dgo[idx];
scierr = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]);
if (scierr == 0)
err = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]);
if (!err)
printf("\t- DGO %.2x: %.8x\n", dgo_id, data[0]);
else
printf("Failed to read DGO %d\n", dgo_id);

13
arch/arm/mach-imx/imx8m/Kconfig
View File

@ -124,6 +124,9 @@ config TARGET_IMX8MM_VENICE
select IMX8M_LPDDR4
select GATEWORKS_SC
select MISC
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
config TARGET_KONTRON_MX8MM
bool "Kontron Electronics N80xx"
@ -175,6 +178,9 @@ config TARGET_IMX8MN_VENICE
select IMX8M_LPDDR4
select GATEWORKS_SC
select MISC
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
config TARGET_IMX8MP_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Plus"
@ -232,6 +238,9 @@ config TARGET_IMX8MP_VENICE
select IMX8M_LPDDR4
select GATEWORKS_SC
select MISC
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
@ -245,6 +254,10 @@ config TARGET_IMX8MN_VAR_SOM
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
select MISC
select I2C_EEPROM
select DM_ETH_PHY
select NVMEM
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"

1
arch/arm/mach-imx/imx8m/clock_imx8mm.c
View File

@ -90,7 +90,6 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq)
case ANATOP_DRAM_PLL:
setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
pll_base = &ana_pll->dram_pll_gnrl_ctl;
break;

4
arch/arm/mach-imx/imx8m/soc.c
View File

@ -737,7 +737,7 @@ static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int siz
if (nodeoff < 0)
continue; /* Not found, skip it */
printf("Found %s node\n", nodes_path[i]);
debug("Found %s node\n", nodes_path[i]);
add_status:
rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
@ -1266,7 +1266,7 @@ int ft_system_setup(void *blob, struct bd_info *bd)
if (nodeoff >= 0) {
const char *speed = "high-speed";
printf("Found %s node\n", usb_dwc3_path[v]);
debug("Found %s node\n", usb_dwc3_path[v]);
usb_modify_speed:

1
arch/arm/mach-imx/imx8ulp/Makefile
View File

@ -5,7 +5,6 @@
obj-y += lowlevel_init.o
obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o
obj-$(CONFIG_AHAB_BOOT) += ahab.o
ifeq ($(CONFIG_SPL_BUILD),y)
obj-y += upower/

18
arch/arm/mach-imx/imx8ulp/rdc.c
View File

@ -9,7 +9,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/mu_hal.h>
#include <asm/mach-imx/s400_api.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/arch/rdc.h>
#include <div64.h>
@ -203,12 +203,12 @@ int xrdc_config_msc(u32 msc, u32 index, u32 dom, u32 perm)
int release_rdc(enum rdc_type type)
{
ulong s_mu_base = 0x27020000UL;
struct sentinel_msg msg;
struct ele_msg msg;
int ret;
u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.version = ELE_VERSION;
msg.tag = ELE_CMD_TAG;
msg.size = 2;
msg.command = ELE_RELEASE_RDC_REQ;
msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */
@ -266,7 +266,7 @@ void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access)
mrgd[4] |= ((access & 0xFFF) << 16);
}
/* not handle other cases, since S400 only set ACCESS1 and 2 */
/* not handle other cases, since ELE only set ACCESS1 and 2 */
writel(mrgd[4], xrdc_base + off + 0x10);
return;
}
@ -295,7 +295,7 @@ void xrdc_init_mda(void)
void xrdc_init_mrc(void)
{
/* Re-config MRC3 for SRAM0 in case protected by S400 */
/* Re-config MRC3 for SRAM0 in case protected by ELE */
xrdc_config_mrc_w0_w1(3, 0, 0x22010000, 0x10000);
xrdc_config_mrc_dx_perm(3, 0, 0, 1);
xrdc_config_mrc_dx_perm(3, 0, 1, 1);
@ -320,7 +320,7 @@ void xrdc_init_mrc(void)
xrdc_config_mrc_dx_perm(5, 0, 1, 1);
xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF);
/* Set MRC6 for DDR access from Sentinel */
/* Set MRC6 for DDR access from ELE */
xrdc_config_mrc_w0_w1(6, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
xrdc_config_mrc_dx_perm(6, 0, 4, 1);
xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
@ -404,7 +404,7 @@ int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_acc
val &= ~(0xFU << offset);
/* MBC0-3
* Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
* Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
* So select MBC0_MEMN_GLBAC0
*/
if (sec_access) {
@ -445,7 +445,7 @@ int trdc_mrc_region_set_access(u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_en
continue;
/* MRC0,1
* Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
* Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
* So select MRCx_MEMN_GLBAC0
*/
if (sec_access) {

16
arch/arm/mach-imx/imx8ulp/soc.c
View File

@ -14,7 +14,7 @@
#include <event.h>
#include <spl.h>
#include <asm/arch/rdc.h>
#include <asm/mach-imx/s400_api.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/mu_hal.h>
#include <cpu_func.h>
#include <asm/setup.h>
@ -70,7 +70,7 @@ int mmc_get_env_dev(void)
}
#endif
static void set_cpu_info(struct sentinel_get_info_data *info)
static void set_cpu_info(struct ele_get_info_data *info)
{
gd->arch.soc_rev = info->soc;
gd->arch.lifecycle = info->lc;
@ -582,9 +582,9 @@ void get_board_serial(struct tag_serialnr *serialnr)
u32 res;
int ret;
ret = ahab_read_common_fuse(1, uid, 4, &res);
ret = ele_read_common_fuse(1, uid, 4, &res);
if (ret)
printf("ahab read fuse failed %d, 0x%x\n", ret, res);
printf("ele read fuse failed %d, 0x%x\n", ret, res);
else
printf("UID 0x%x,0x%x,0x%x,0x%x\n", uid[0], uid[1], uid[2], uid[3]);
@ -783,7 +783,7 @@ int imx8ulp_dm_post_init(void)
struct udevice *devp;
int ret;
u32 res;
struct sentinel_get_info_data *info = (struct sentinel_get_info_data *)SRAM0_BASE;
struct ele_get_info_data *info = (struct ele_get_info_data *)SRAM0_BASE;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8ulp_mu), &devp);
if (ret) {
@ -791,11 +791,11 @@ int imx8ulp_dm_post_init(void)
return ret;
}
ret = ahab_get_info(info, &res);
ret = ele_get_info(info, &res);
if (ret) {
printf("ahab_get_info failed %d\n", ret);
printf("ele_get_info failed %d\n", ret);
/* fallback to A0.1 revision */
memset((void *)info, 0, sizeof(struct sentinel_get_info_data));
memset((void *)info, 0, sizeof(struct ele_get_info_data));
info->soc = 0xa000084d;
}

6
arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
View File

@ -217,8 +217,8 @@ int upower_init(void)
* CM33 Cache
* PowerQuad RAM
* ETF RAM
* Sentinel PKC, Data RAM1, Inst RAM0/1
* Sentinel ROM
* ELE PKC, Data RAM1, Inst RAM0/1
* ELE ROM
* uPower IRAM/DRAM
* uPower ROM
* CM33 ROM
@ -230,7 +230,7 @@ int upower_init(void)
* SSRAM Partition 7_a(128KB)
* SSRAM Partition 7_b(64KB)
* SSRAM Partition 7_c(64KB)
* Sentinel Data RAM0, Inst RAM2
* ELE Data RAM0, Inst RAM2
*/
/* MIPI-CSI FIFO BIT28 not set */
memon = 0x3FFFFFEFFFFFFCUL;

8
arch/arm/mach-imx/imx9/clock.c
View File

@ -709,8 +709,8 @@ struct imx_clk_setting imx_clk_settings[] = {
/* Set A55 mtr bus to 133M */
{ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Sentinel to 133M */
{SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* ELE to 133M */
{ELE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Bus_wakeup to 133M */
{BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Bus_AON to 133M */
@ -740,8 +740,8 @@ struct imx_clk_setting imx_clk_settings[] = {
{ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3},
/* Set A55 mtr bus to 133M */
{ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Sentinel to 200M */
{SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
/* ELE to 200M */
{ELE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
/* Bus_wakeup to 133M */
{BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Bus_AON to 133M */

2
arch/arm/mach-imx/imx9/clock_root.c
View File

@ -34,7 +34,7 @@ static struct clk_root_map clk_root_array[] = {
{ ARM_A55_MTR_BUS_CLK_ROOT, 2 },
{ ARM_A55_CLK_ROOT, 0 },
{ M33_CLK_ROOT, 2 },
{ SENTINEL_CLK_ROOT, 2 },
{ ELE_CLK_ROOT, 2 },
{ BUS_WAKEUP_CLK_ROOT, 2 },
{ BUS_AON_CLK_ROOT, 2 },
{ WAKEUP_AXI_CLK_ROOT, 0 },

6
arch/arm/mach-imx/imx9/imx_bootaux.c
View File

@ -13,7 +13,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
{
struct arm_smccc_res res;
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0,
0, 0, 0, 0, &res);
return res.a0;
@ -25,7 +25,7 @@ int arch_auxiliary_core_down(u32 core_id)
printf("## Stopping auxiliary core\n");
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STOP, 0, 0,
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STOP, 0, 0,
0, 0, 0, 0, &res);
return 0;
@ -40,7 +40,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
printf("## Starting auxiliary core addr = 0x%08lX...\n", addr);
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, addr, 0,
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, addr, 0,
0, 0, 0, 0, &res);
return 0;

44
arch/arm/mach-imx/imx9/soc.c
View File

@ -34,7 +34,7 @@
#include <asm/setup.h>
#include <asm/bootm.h>
#include <asm/arch-imx/cpu.h>
#include <asm/mach-imx/s400_api.h>
#include <asm/mach-imx/ele_api.h>
#include <fuse.h>
#include <asm/arch/ddr.h>
@ -151,7 +151,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
return val;
}
static void set_cpu_info(struct sentinel_get_info_data *info)
static void set_cpu_info(struct ele_get_info_data *info)
{
gd->arch.soc_rev = info->soc;
gd->arch.lifecycle = info->lc;
@ -557,7 +557,7 @@ int imx9_probe_mu(void *ctx, struct event *event)
struct udevice *devp;
int node, ret;
u32 res;
struct sentinel_get_info_data info;
struct ele_get_info_data info;
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4");
@ -568,7 +568,7 @@ int imx9_probe_mu(void *ctx, struct event *event)
if (gd->flags & GD_FLG_RELOC)
return 0;
ret = ahab_get_info(&info, &res);
ret = ele_get_info(&info, &res);
if (ret)
return ret;
@ -600,35 +600,31 @@ int timer_init(void)
enum env_location env_get_location(enum env_operation op, int prio)
{
enum boot_device dev = get_boot_device();
enum env_location env_loc = ENVL_UNKNOWN;
if (prio)
return env_loc;
return ENVL_UNKNOWN;
switch (dev) {
#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
case QSPI_BOOT:
env_loc = ENVL_SPI_FLASH;
break;
#endif
#if defined(CONFIG_ENV_IS_IN_MMC)
if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
return ENVL_SPI_FLASH;
return ENVL_NOWHERE;
case SD1_BOOT:
case SD2_BOOT:
case SD3_BOOT:
case MMC1_BOOT:
case MMC2_BOOT:
case MMC3_BOOT:
env_loc = ENVL_MMC;
break;
#endif
if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
return ENVL_MMC;
else if (CONFIG_IS_ENABLED(ENV_IS_IN_EXT4))
return ENVL_EXT4;
else if (CONFIG_IS_ENABLED(ENV_IS_IN_FAT))
return ENVL_FAT;
return ENVL_NOWHERE;
default:
#if defined(CONFIG_ENV_IS_NOWHERE)
env_loc = ENVL_NOWHERE;
#endif
break;
return ENVL_NOWHERE;
}
return env_loc;
}
static int mix_power_init(enum mix_power_domain pd)
@ -646,7 +642,7 @@ static int mix_power_init(enum mix_power_domain pd)
mem_id = SRC_MEM_MEDIA;
scr = BIT(5);
/* Enable S400 handshake */
/* Enable ELE handshake */
struct blk_ctrl_s_aonmix_regs *s_regs =
(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
@ -763,8 +759,8 @@ int m33_prepare(void)
while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT))
val = readl(&mix_regs->func_stat);
/* Release Sentinel TROUT */
ahab_release_m33_trout();
/* Release ELE TROUT */
ele_release_m33_trout();
/* Mask WDOG1 IRQ from A55, we use it for M33 reset */
setbits_le32(&s_regs->ca55_irq_mask[1], BIT(6));
@ -772,7 +768,7 @@ int m33_prepare(void)
/* Turn on WDOG1 clock */
ccm_lpcg_on(CCGR_WDG1, 1);
/* Set sentinel LP handshake for M33 reset */
/* Set ELE LP handshake for M33 reset */
setbits_le32(&s_regs->lp_handshake[0], BIT(6));
/* Clear M33 TCM for ECC */

14
arch/arm/mach-imx/imx9/trdc.c
View File

@ -10,7 +10,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <div64.h>
#include <asm/mach-imx/s400_api.h>
#include <asm/mach-imx/ele_api.h>
#include <asm/mach-imx/mu_hal.h>
#define DID_NUM 16
@ -196,7 +196,7 @@ int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x,
val &= ~(0xFU << offset);
/* MBC0-3
* Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
* Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
* So select MBC0_MEMN_GLBAC0
*/
if (sec_access) {
@ -266,7 +266,7 @@ int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32 addr_start,
continue;
/* MRC0,1
* Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
* Global 0, 0x7777 secure pri/user read/write/execute, ELE has already set it.
* So select MRCx_MEMN_GLBAC0
*/
if (sec_access) {
@ -315,7 +315,7 @@ bool trdc_mbc_enabled(ulong trdc_base)
int release_rdc(u8 xrdc)
{
ulong s_mu_base = 0x47520000UL;
struct sentinel_msg msg;
struct ele_msg msg;
int ret;
u32 rdc_id;
@ -336,8 +336,8 @@ int release_rdc(u8 xrdc)
return -EINVAL;
}
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.version = ELE_VERSION;
msg.tag = ELE_CMD_TAG;
msg.size = 2;
msg.command = ELE_RELEASE_RDC_REQ;
msg.data[0] = (rdc_id << 8) | 0x2; /* A55 */
@ -394,7 +394,7 @@ void trdc_init(void)
/* DDR */
trdc_mrc_set_control(0x49010000, 0, 0, 0x7777);
/* S400*/
/* ELE */
trdc_mrc_region_config(0x49010000, 0, 0, 0x80000000, 0xFFFFFFFF, false, 0);
/* MTR */

45
arch/arm/mach-imx/imx_bootaux.c
View File

@ -14,6 +14,7 @@
#include <linux/compiler.h>
#include <cpu_func.h>
#ifndef CONFIG_IMX8
/* Just to avoid build error */
#if IS_ENABLED(CONFIG_IMX8M)
#define SRC_M4C_NON_SCLR_RST_MASK BIT(0)
@ -45,7 +46,7 @@ static const struct rproc_att *get_host_mapping(unsigned long auxcore)
* is valid, returns the entry point address.
* Translates load addresses in the elf file to the U-Boot address space.
*/
static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong *stack)
static u32 load_elf_image_m_core_phdr(unsigned long addr, u32 *stack)
{
Elf32_Ehdr *ehdr; /* ELF header structure pointer */
Elf32_Phdr *phdr; /* Program header structure pointer */
@ -95,7 +96,7 @@ static unsigned long load_elf_image_m_core_phdr(unsigned long addr, ulong *stack
int arch_auxiliary_core_up(u32 core_id, ulong addr)
{
ulong stack, pc;
u32 stack, pc;
if (!addr)
return -EINVAL;
@ -121,18 +122,18 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
pc = *(u32 *)(addr + 4);
}
printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n",
stack, pc);
/* Set the stack and pc to M4 bootROM */
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
/* Set the stack and pc to MCU bootROM */
writel(stack, MCU_BOOTROM_BASE_ADDR);
writel(pc, MCU_BOOTROM_BASE_ADDR + 4);
flush_dcache_all();
/* Enable M4 */
/* Enable MCU */
if (IS_ENABLED(CONFIG_IMX8M)) {
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL);
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0, 0, 0, 0, 0, NULL);
} else {
clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
@ -147,7 +148,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
unsigned int val;
if (IS_ENABLED(CONFIG_IMX8M)) {
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res);
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0, 0, 0, 0, 0, &res);
return res.a0;
}
@ -158,30 +159,34 @@ int arch_auxiliary_core_check_up(u32 core_id)
return 1;
}
#endif
/*
* To i.MX6SX and i.MX7D, the image supported by bootaux needs
* the reset vector at the head for the image, with SP and PC
* as the first two words.
*
* Per the cortex-M reference manual, the reset vector of M4 needs
* to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
* of that vector. So to boot M4, the A core must build the M4's reset
* Per the cortex-M reference manual, the reset vector of M4/M7 needs
* to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses
* of that vector. So to boot M4/M7, the A core must build the M4/M7's reset
* vector with getting the PC and SP from image and filling them to
* TCMUL. When M4 is kicked, it will load the PC and SP by itself.
* The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
* accessing the M4 TCMUL.
* TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself.
* The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for
* accessing the M4/M7 TCMUL/IDTCM.
*/
static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
ulong addr;
int ret, up;
u32 core = 0;
if (argc < 2)
return CMD_RET_USAGE;
up = arch_auxiliary_core_check_up(0);
if (argc > 2)
core = simple_strtoul(argv[2], NULL, 10);
up = arch_auxiliary_core_check_up(core);
if (up) {
printf("## Auxiliary core is already up\n");
return CMD_RET_SUCCESS;
@ -192,7 +197,7 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
if (!addr)
return CMD_RET_FAILURE;
ret = arch_auxiliary_core_up(0, addr);
ret = arch_auxiliary_core_up(core, addr);
if (ret)
return CMD_RET_FAILURE;
@ -202,5 +207,7 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
U_BOOT_CMD(
bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
"Start auxiliary core",
""
"<address> [<core>]\n"
" - start auxiliary core [<core>] (default 0),\n"
" at address <address>\n"
);

2
arch/arm/mach-imx/mx6/module_fuse.c
View File

@ -206,7 +206,7 @@ int ft_system_setup(void *blob, struct bd_info *bd)
if (off < 0)
continue; /* Not found, skip it */
add_status:
rc = fdt_setprop(blob, nodeoff, "status", status,
rc = fdt_setprop(blob, off, "status", status,
strlen(status) + 1);
if (rc) {
if (rc == -FDT_ERR_NOSPACE) {

23
arch/arm/mach-imx/mxs/Kconfig
View File

@ -10,10 +10,12 @@ choice
config TARGET_MX23_OLINUXINO
bool "Support mx23_olinuxino"
select PL01X_SERIAL
select BOARD_EARLY_INIT_F
config TARGET_MX23EVK
bool "Support mx23evk"
select PL01X_SERIAL
select BOARD_EARLY_INIT_F
config TARGET_XFI3
@ -41,16 +43,37 @@ choice
config TARGET_MX28EVK
bool "Support mx28evk"
select PL01X_SERIAL
select BOARD_EARLY_INIT_F
config TARGET_XEA
bool "Support XEA"
select PL01X_SERIAL
endchoice
config SYS_SOC
default "mxs"
config SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT
bool "Force minimal current draw from VDD5V by MX28 PMU"
default n
help
After setting this option, the current drawn from VDD5V
by the PMU is reduced to zero - the DCDC_BATT is used as
the main power source for PMU.
config SPL_MXS_PMU_DISABLE_BATT_CHARGE
bool "Disable Battery Charging in MX28 PMU"
default n
config SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR
bool "Enable the 4P2 linear regulator in MX28 PMU"
default y
help
This option enables the 4P2 linear regulator (derived
from VDD5V) - so the VDD4P2 power source is operational.
source "board/freescale/mx28evk/Kconfig"
source "board/liebherr/xea/Kconfig"

119
arch/arm/mach-imx/parse-container.c
View File

@ -1,75 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018-2019 NXP
* Copyright 2018-2021 NXP
*/
#include <common.h>
#include <stdlib.h>
#include <errno.h>
#include <log.h>
#include <spl.h>
#include <asm/mach-imx/image.h>
#ifdef CONFIG_AHAB_BOOT
#include <firmware/imx/sci/sci.h>
#endif
#define SEC_SECURE_RAM_BASE 0x31800000UL
#define SEC_SECURE_RAM_END_BASE (SEC_SECURE_RAM_BASE + 0xFFFFUL)
#define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE 0x60000000UL
#define SECO_PT 2U
#ifdef CONFIG_AHAB_BOOT
static int authenticate_image(struct boot_img_t *img, int image_index)
{
sc_faddr_t start, end;
sc_rm_mr_t mr;
int err;
int ret = 0;
debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n",
image_index, (uint32_t)img->dst, img->offset, img->size);
/* Find the memreg and set permission for seco pt */
err = sc_rm_find_memreg(-1, &mr,
img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1);
if (err) {
printf("can't find memreg for image %d load address 0x%x, error %d\n",
image_index, img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), err);
return -ENOMEM;
}
err = sc_rm_get_memreg_info(-1, mr, &start, &end);
if (!err)
debug("memreg %u 0x%x -- 0x%x\n", mr, start, end);
err = sc_rm_set_memreg_permissions(-1, mr,
SECO_PT, SC_RM_PERM_FULL);
if (err) {
printf("set permission failed for img %d, error %d\n",
image_index, err);
return -EPERM;
}
err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
1 << image_index);
if (err) {
printf("authenticate img %d failed, return %d\n",
image_index, err);
ret = -EIO;
}
err = sc_rm_set_memreg_permissions(-1, mr,
SECO_PT, SC_RM_PERM_NONE);
if (err) {
printf("remove permission failed for img %d, error %d\n",
image_index, err);
ret = -EPERM;
}
return ret;
}
#include <asm/mach-imx/ahab.h>
#endif
static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image,
@ -110,10 +51,8 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image,
}
#ifdef CONFIG_AHAB_BOOT
if (authenticate_image(&images[image_index], image_index)) {
printf("Failed to authenticate image %d\n", image_index);
if (ahab_verify_cntr_image(&images[image_index], image_index))
return NULL;
}
#endif
return &images[image_index];
@ -134,21 +73,27 @@ static int read_auth_container(struct spl_image_info *spl_image,
* It will not override the ATF code, so safe to use it here,
* no need malloc
*/
container = (struct container_hdr *)spl_get_load_buffer(-size, size);
container = malloc(size);
if (!container)
return -ENOMEM;
debug("%s: container: %p sector: %lu sectors: %u\n", __func__,
container, sector, sectors);
if (info->read(info, sector, sectors, container) != sectors)
return -EIO;
if (info->read(info, sector, sectors, container) != sectors) {
ret = -EIO;
goto end;
}
if (container->tag != 0x87 && container->version != 0x0) {
printf("Wrong container header\n");
return -ENOENT;
printf("Wrong container header");
ret = -ENOENT;
goto end;
}
if (!container->num_images) {
printf("Wrong container, no image found\n");
return -ENOENT;
printf("Wrong container, no image found");
ret = -ENOENT;
goto end;
}
length = container->length_lsb + (container->length_msb << 8);
@ -158,25 +103,24 @@ static int read_auth_container(struct spl_image_info *spl_image,
size = roundup(length, info->bl_len);
sectors = size / info->bl_len;
container = (struct container_hdr *)spl_get_load_buffer(-size, size);
free(container);
container = malloc(size);
if (!container)
return -ENOMEM;
debug("%s: container: %p sector: %lu sectors: %u\n",
__func__, container, sector, sectors);
if (info->read(info, sector, sectors, container) !=
sectors)
return -EIO;
sectors) {
ret = -EIO;
goto end;
}
}
#ifdef CONFIG_AHAB_BOOT
memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container,
ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
ret = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
if (ret) {
printf("authenticate container hdr failed, return %d\n", ret);
return ret;
}
ret = ahab_auth_cntr_hdr(container, length);
if (ret)
goto end_auth;
#endif
for (i = 0; i < container->num_images; i++) {
@ -197,9 +141,12 @@ static int read_auth_container(struct spl_image_info *spl_image,
end_auth:
#ifdef CONFIG_AHAB_BOOT
if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0))
printf("Error: release container failed!\n");
ahab_auth_release();
#endif
end:
free(container);
return ret;
}

10
arch/arm/mach-imx/priblob.c
View File

@ -13,12 +13,16 @@
#include <asm/io.h>
#include <common.h>
#include <command.h>
#include "../drivers/crypto/fsl_caam_internal.h"
#include <fsl_sec.h>
int do_priblob_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
{
writel((readl(CAAM_SCFGR) & 0xFFFFFFFC) | 3, CAAM_SCFGR);
printf("New priblob setting = 0x%x\n", readl(CAAM_SCFGR) & 0x3);
ccsr_sec_t *sec_regs = (ccsr_sec_t *)CAAM_BASE_ADDR;
u32 scfgr = sec_in32(&sec_regs->scfgr);
scfgr |= 0x3;
sec_out32(&sec_regs->scfgr, scfgr);
printf("New priblob setting = 0x%x\n", sec_in32(&sec_regs->scfgr) & 0x3);
return 0;
}

32
arch/arm/mach-imx/spl_imx_romapi.c
View File

@ -76,13 +76,16 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image,
u32 image_offset;
ret = rom_api_query_boot_infor(QUERY_IVT_OFF, &offset);
ret |= rom_api_query_boot_infor(QUERY_PAGE_SZ, &pagesize);
ret |= rom_api_query_boot_infor(QUERY_IMG_OFF, &image_offset);
if (ret != ROM_API_OKAY)
goto err;
if (ret != ROM_API_OKAY) {
puts("ROMAPI: Failure query boot infor pagesize/offset\n");
return -1;
}
ret = rom_api_query_boot_infor(QUERY_PAGE_SZ, &pagesize);
if (ret != ROM_API_OKAY)
goto err;
ret = rom_api_query_boot_infor(QUERY_IMG_OFF, &image_offset);
if (ret != ROM_API_OKAY)
goto err;
header = (struct legacy_img_hdr *)(CONFIG_SPL_IMX_ROMAPI_LOADADDR);
@ -124,6 +127,10 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image,
}
return 0;
err:
puts("ROMAPI: Failure query boot infor pagesize/offset\n");
return -1;
}
static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
@ -344,12 +351,12 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
u32 boot, bstage;
ret = rom_api_query_boot_infor(QUERY_BT_DEV, &boot);
ret |= rom_api_query_boot_infor(QUERY_BT_STAGE, &bstage);
if (ret != ROM_API_OKAY)
goto err;
if (ret != ROM_API_OKAY) {
puts("ROMAPI: failure at query_boot_info\n");
return -1;
}
ret = rom_api_query_boot_infor(QUERY_BT_STAGE, &bstage);
if (ret != ROM_API_OKAY)
goto err;
printf("Boot Stage: ");
@ -374,4 +381,7 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
return spl_romapi_load_image_stream(spl_image, bootdev);
return spl_romapi_load_image_seekable(spl_image, bootdev, boot);
err:
puts("ROMAPI: failure at query_boot_info\n");
return -1;
}

6
board/advantech/imx8qm_dmsse20_a1/spl.c
View File

@ -111,7 +111,7 @@ int board_mmc_init(struct bd_info *bis)
switch (i) {
case 0:
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
if (ret != SC_ERR_NONE)
if (ret)
return ret;
imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
@ -120,10 +120,10 @@ int board_mmc_init(struct bd_info *bis)
break;
case 1:
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
if (ret != SC_ERR_NONE)
if (ret)
return ret;
ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
if (ret != SC_ERR_NONE)
if (ret)
return ret;
imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));

6
board/advantech/imx8qm_rom7720_a1/spl.c
View File

@ -112,7 +112,7 @@ int board_mmc_init(struct bd_info *bis)
switch (i) {
case 0:
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
if (ret != SC_ERR_NONE)
if (ret)
return ret;
imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
@ -121,10 +121,10 @@ int board_mmc_init(struct bd_info *bis)
break;
case 1:
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
if (ret != SC_ERR_NONE)
if (ret)
return ret;
ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
if (ret != SC_ERR_NONE)
if (ret)
return ret;
imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));

1
board/beacon/imx8mm/MAINTAINERS
View File

@ -5,3 +5,4 @@ S: Maintained
F: board/beacon/imx8mm/
F: include/configs/imx8mm_beacon.h
F: configs/imx8mm_beacon_defconfig
F: doc/board/beacon/

37
board/beacon/imx8mm/README
View File

@ -1,37 +0,0 @@
U-Boot for the Beacon EmbeddedWorks Devkit
Quick Start
===========
- Build the ARM Trusted firmware binary
- Get ddr firmware
- Build U-Boot
- Boot
Get and Build the ARM Trusted firmware
======================================
Note: $(srctree) is U-Boot source directory
$ git clone https://github.com/nxp-imx/imx-atf
$ git lf-5.10.72-2.2.0
$ make PLAT=imx8mm bl31 CROSS_COMPILE=aarch64-linux-gnu-
$ cp build/imx8mm/release/bl31.bin $(srctree)
Get the DDR firmware
====================
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
$ chmod +x firmware-imx-8.9.bin
$ ./firmware-imx-8.9
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
Build U-Boot
============
$ make imx8mm_beacon_defconfig
$ make CROSS_COMPILE=aarch64-linux-gnu-
Burn U-Boot to microSD Card
===========================
$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
Boot
====
Set Boot switch to SD boot

19
board/beacon/imx8mm/imx8mm_beacon.env Normal file
View File

@ -0,0 +1,19 @@
boot_fit=try
bootscript=echo Running bootscript from mmc ...; source
console=ttymxc1
fdt_addr=0x45000000
fdt_file=imx8mm-beacon-kit.dtb
finduuid=part uuid mmc ${mmcdev}:2 uuid
image=Image
initrd_addr=0x46000000
loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
mmcargs=setenv bootargs console=${console},${baudrate} root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}
mmcautodetect=yes
mmcboot=echo Booting from mmc ...; run finduuid; run mmcargs; if run loadfdt; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi;
netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
mmcdev=1
mmcpart=1
netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${loadaddr} ${image}; if test ${boot_fit} = yes || test ${boot_fit} = try; then bootm ${loadaddr}; else if ${get_cmd} ${fdt_addr} ${fdt_file}; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; fi;
script=boot.scr

7
board/beacon/imx8mm/spl.c
View File

@ -36,6 +36,8 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
return BOOT_DEVICE_MMC2;
case USB_BOOT:
return BOOT_DEVICE_BOARD;
case QSPI_BOOT:
return BOOT_DEVICE_NOR;
default:
return BOOT_DEVICE_NONE;
}
@ -46,6 +48,11 @@ static void spl_dram_init(void)
ddr_init(&dram_timing);
}
void spl_board_init(void)
{
arch_misc_init();
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{

38
board/beacon/imx8mn/README
View File

@ -1,38 +0,0 @@
U-Boot for the Beacon EmbeddedWorks i.MX8M Nano Devkit
Quick Start
===========
- Build the ARM Trusted firmware binary
- Get ddr firmware
- Build U-Boot
- Boot
Get and Build the ARM Trusted firmware
======================================
Note: $(srctree) is U-Boot source directory
$ git clone https://github.com/nxp-imx/imx-atf
$ git lf-5.10.72-2.2.0
$ make PLAT=imx8mn bl31 CROSS_COMPILE=aarch64-linux-gnu-
$ cp build/imx8mn/release/bl31.bin $(srctree)
Get the DDR firmware
====================
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
$ chmod +x firmware-imx-8.9.bin
$ ./firmware-imx-8.9
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
Build U-Boot
============
$ make imx8mn_beacon_defconfig
$ make CROSS_COMPILE=aarch64-linux-gnu-
Burn U-Boot to microSD Card
===========================
$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
Boot
====
Set baseboard DIP switch:
S17: 1100XXXX

25
board/beacon/imx8mn/imx8mn_beacon.env Normal file
View File

@ -0,0 +1,25 @@
boot_fdt=try
bootdelay=2
bootscript=echo Running bootscript from mmc ...; source
console=ttymxc1
fdt_addr=0x45000000
fdt_file=imx8mn-beacon-kit.dtb
finduuid=part uuid mmc ${mmcdev}:2 uuid
image=Image
initrd_addr=0x46000000
loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
loadramdisk=load mmc ${mmcdev} ${ramdisk_addr} ${ramdiskimage}
mmcargs=setenv bootargs console=${console},${baudrate} root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}
mmcautodetect=yes
mmcboot=echo Booting from mmc ...; run finduuid; run mmcargs; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if run loadfdt; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; else echo wait for boot; fi;
mmcdev=1
mmcpart=1
netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
netboot=echo Booting from net ...; run netargs; if test ${ip_dyn} = yes; then setenv get_cmd dhcp; else setenv get_cmd tftp; fi; ${get_cmd} ${loadaddr} ${image}; if test ${boot_fdt} = yes || test ${boot_fdt} = try; then if ${get_cmd} ${fdt_addr} ${fdt_file}; then booti ${loadaddr} - ${fdt_addr}; else echo WARN: Cannot load the DT; fi; else booti; fi;
ramargs=setenv bootargs console=${console},${baudrate} root=/dev/ram rw ${optargs}
ramboot=echo Booting from RAMdisk...; run loadimage; run loadfdt; fdt addr $fdt_addr; run loadramdisk; run ramargs; booti ${loadaddr} ${ramdisk_addr} ${fdt_addr} ${optargs}
ramdisk_addr=0x46000000
ramdiskimage=rootfs.cpio.uboot
script=boot.scr

8
board/congatec/cgtqmx8/cgtqmx8.c
View File

@ -79,7 +79,7 @@ static void setup_iomux_uart(void)
int board_early_init_f(void)
{
/* sc_ipc_t ipcHndl = 0; */
sc_err_t scierr = 0;
int scierr;
/* When start u-boot in XEN VM, directly return */
/* if (IS_ENABLED(CONFIG_XEN)) */
@ -89,19 +89,19 @@ int board_early_init_f(void)
/* Power up UART0, this is very early while power domain is not working */
scierr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
if (scierr != SC_ERR_NONE)
if (scierr)
return 0;
/* Set UART0 clock root to 80 MHz */
sc_pm_clock_rate_t rate = 80000000;
scierr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
if (scierr != SC_ERR_NONE)
if (scierr)
return 0;
/* Enable UART0 clock root */
scierr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
if (scierr != SC_ERR_NONE)
if (scierr)
return 0;
setup_iomux_uart();

14
board/data_modul/imx8mp_edm_sbc/spl.c
View File

@ -107,6 +107,20 @@ void board_boot_order(u32 *spl_boot_list)
spl_boot_list[4] = BOOT_DEVICE_NONE;
}
unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long sect)
{
const u32 boot_dev = spl_boot_device();
int part;
if (boot_dev == BOOT_DEVICE_MMC2) { /* eMMC */
part = spl_mmc_emmc_boot_partition(mmc);
if (part == 1 || part == 2) /* eMMC BOOT1/BOOT2 HW partitions */
return sect - 0x40;
}
return sect;
}
static struct dram_timing_info *dram_timing_info[8] = {
&dmo_imx8mp_sbc_dram_timing_32_32, /* 32 Gbit x32 */
NULL, /* 32 Gbit x16 */

20
board/freescale/imx8ulp_evk/spl.c
View File

@ -19,7 +19,7 @@
#include <asm/arch/ddr.h>
#include <asm/arch/rdc.h>
#include <asm/arch/upower.h>
#include <asm/mach-imx/s400_api.h>
#include <asm/mach-imx/ele_api.h>
DECLARE_GLOBAL_DATA_PTR;
@ -63,9 +63,9 @@ void display_ele_fw_version(void)
u32 fw_version, sha1, res;
int ret;
ret = ahab_get_fw_version(&fw_version, &sha1, &res);
ret = ele_get_fw_version(&fw_version, &sha1, &res);
if (ret) {
printf("ahab get firmware version failed %d, 0x%x\n", ret, res);
printf("ele get firmware version failed %d, 0x%x\n", ret, res);
} else {
printf("ELE firmware version %u.%u.%u-%x",
(fw_version & (0x00ff0000)) >> 16,
@ -120,9 +120,19 @@ void spl_board_init(void)
set_lpav_qos();
/* Enable A35 access to the CAAM */
ret = ahab_release_caam(0x7, &res);
ret = ele_release_caam(0x7, &res);
if (ret)
printf("ahab release caam failed %d, 0x%x\n", ret, res);
printf("ele release caam failed %d, 0x%x\n", ret, res);
/*
* RNG start only available on the A1 soc revision.
* Check some JTAG register for the SoC revision.
*/
if (!is_soc_rev(CHIP_REV_1_0)) {
ret = ele_start_rng();
if (ret)
printf("Fail to start RNG: %d\n", ret);
}
}
void board_init_f(ulong dummy)

1
board/freescale/imx93_evk/spl.c
View File

@ -20,7 +20,6 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch-mx7ulp/gpio.h>
#include <asm/mach-imx/syscounter.h>
#include <asm/mach-imx/s400_api.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>

6
board/freescale/mx7dsabresd/mx7dsabresd.c
View File

@ -292,6 +292,7 @@ int power_init_board(void)
int board_late_init(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
unsigned char eth1addr[6];
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
@ -303,6 +304,11 @@ int board_late_init(void)
*/
clrsetbits_le16(&wdog->wcr, 0, 0x10);
/* Get the second MAC address */
imx_get_mac_from_fuse(1, eth1addr);
if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
eth_env_set_enetaddr("eth1addr", eth1addr);
return 0;
}

5
board/gateworks/venice/eeprom.c
View File

@ -218,6 +218,11 @@ const char *eeprom_get_dtb_name(int level, char *buf, int sz)
int rev_base_bom = get_bom_rev(base_info.model);
snprintf(buf, sz, "%s%2dxx-%dx", pre, base, som);
/* GW79xx baseboards have no build options */
if (base == 79) {
base = (int)strtoul(base_info.model + 2, NULL, 10);
snprintf(buf, sz, "%s%4d-%dx", pre, base, som);
}
switch (level) {
case 0: /* full model (ie gw73xx-0x-a1a1) */
if (rev_base_bom)

1
board/gateworks/venice/lpddr4_timing.h
View File

@ -16,6 +16,7 @@ extern struct dram_timing_info dram_timing_1gb_single_die;
extern struct dram_timing_info dram_timing_2gb_single_die;
extern struct dram_timing_info dram_timing_2gb_dual_die;
#elif CONFIG_IMX8MP
extern struct dram_timing_info dram_timing_1gb_single_die;
extern struct dram_timing_info dram_timing_4gb_dual_die;
#endif

532
board/gateworks/venice/lpddr4_timing_imx8mp.c
View File

@ -1314,6 +1314,538 @@ static struct dram_cfg_param ddr_phy_pie[] = {
{ 0xd0000, 0x1 }
};
/*
* Generated code from MX8M_DDR_tool v3.30 using MX8MP Plus RPAv9
* - 1GiB: ixm8mp-gw7020 1x Micron MT53E256M32D2DS 2-ch single-die per channel
*/
struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = {
/** Initialize DDRC registers **/
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa1080020 },
{ 0x3d400020, 0x1203 },
{ 0x3d400024, 0x16e3600 },
{ 0x3d400064, 0x5b0087 },
{ 0x3d400070, 0x7027f90 },
{ 0x3d400074, 0x790 },
{ 0x3d4000d0, 0xc00305ba },
{ 0x3d4000d4, 0x940000 },
{ 0x3d4000dc, 0xd4002d },
{ 0x3d4000e0, 0x310000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
{ 0x3d400100, 0x191e1920 },
{ 0x3d400104, 0x60630 },
{ 0x3d40010c, 0xb0b000 },
{ 0x3d400110, 0xe04080e },
{ 0x3d400114, 0x2040c0c },
{ 0x3d400118, 0x1010007 },
{ 0x3d40011c, 0x402 },
{ 0x3d400130, 0x20600 },
{ 0x3d400134, 0xc100002 },
{ 0x3d400138, 0x8d },
{ 0x3d400144, 0x96004b },
{ 0x3d400180, 0x2ee0017 },
{ 0x3d400184, 0x2605b8e },
{ 0x3d400188, 0x0 },
{ 0x3d400190, 0x497820a },
{ 0x3d400194, 0x80303 },
{ 0x3d4001b4, 0x170a },
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001b0, 0x11 },
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0x699 },
{ 0x3d400108, 0x70e1617 },
{ 0x3d400200, 0x1f },
{ 0x3d400208, 0x0 },
{ 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f },
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0xf070707 },
{ 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x1705 },
{ 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 },
{ 0x3d400264, 0x900093e7 },
{ 0x3d40026c, 0x2005574 },
{ 0x3d400400, 0x111 },
{ 0x3d400404, 0x72ff },
{ 0x3d400408, 0x72ff },
{ 0x3d400494, 0x2100e07 },
{ 0x3d400498, 0x620096 },
{ 0x3d40049c, 0x1100e07 },
{ 0x3d4004a0, 0xc8012c },
{ 0x3d402020, 0x1001 },
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc0012 },
{ 0x3d4020dc, 0x840000 },
{ 0x3d4020e0, 0x330000 },
{ 0x3d4020e8, 0x660048 },
{ 0x3d4020ec, 0x160048 },
{ 0x3d402100, 0xa040305 },
{ 0x3d402104, 0x30407 },
{ 0x3d402108, 0x203060b },
{ 0x3d40210c, 0x505000 },
{ 0x3d402110, 0x2040202 },
{ 0x3d402114, 0x2030202 },
{ 0x3d402118, 0x1010004 },
{ 0x3d40211c, 0x302 },
{ 0x3d402130, 0x20300 },
{ 0x3d402134, 0xa100002 },
{ 0x3d402138, 0x13 },
{ 0x3d402144, 0x14000a },
{ 0x3d402180, 0x640004 },
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
{ 0x3d4020f4, 0x599 },
{ 0x3d403020, 0x1001 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x30005 },
{ 0x3d4030dc, 0x840000 },
{ 0x3d4030e0, 0x330000 },
{ 0x3d4030e8, 0x660048 },
{ 0x3d4030ec, 0x160048 },
{ 0x3d403100, 0xa010102 },
{ 0x3d403104, 0x30404 },
{ 0x3d403108, 0x203060b },
{ 0x3d40310c, 0x505000 },
{ 0x3d403110, 0x2040202 },
{ 0x3d403114, 0x2030202 },
{ 0x3d403118, 0x1010004 },
{ 0x3d40311c, 0x302 },
{ 0x3d403130, 0x20300 },
{ 0x3d403134, 0xa100002 },
{ 0x3d403138, 0x5 },
{ 0x3d403144, 0x50003 },
{ 0x3d403180, 0x190004 },
{ 0x3d403190, 0x3818200 },
{ 0x3d403194, 0x80303 },
{ 0x3d4031b4, 0x100 },
{ 0x3d4030f4, 0x599 },
{ 0x3d400028, 0x0 },
};
/* PHY Initialize Configuration */
struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = {
{ 0x100a0, 0x0 },
{ 0x100a1, 0x1 },
{ 0x100a2, 0x3 },
{ 0x100a3, 0x2 },
{ 0x100a4, 0x5 },
{ 0x100a5, 0x4 },
{ 0x100a6, 0x7 },
{ 0x100a7, 0x6 },
{ 0x110a0, 0x0 },
{ 0x110a1, 0x1 },
{ 0x110a2, 0x2 },
{ 0x110a3, 0x3 },
{ 0x110a4, 0x4 },
{ 0x110a5, 0x5 },
{ 0x110a6, 0x6 },
{ 0x110a7, 0x7 },
{ 0x120a0, 0x0 },
{ 0x120a1, 0x1 },
{ 0x120a2, 0x2 },
{ 0x120a3, 0x3 },
{ 0x120a4, 0x4 },
{ 0x120a5, 0x5 },
{ 0x120a6, 0x6 },
{ 0x120a7, 0x7 },
{ 0x130a0, 0x0 },
{ 0x130a1, 0x1 },
{ 0x130a2, 0x3 },
{ 0x130a3, 0x4 },
{ 0x130a4, 0x5 },
{ 0x130a5, 0x2 },
{ 0x130a6, 0x7 },
{ 0x130a7, 0x6 },
{ 0x1005f, 0x1ff },
{ 0x1015f, 0x1ff },
{ 0x1105f, 0x1ff },
{ 0x1115f, 0x1ff },
{ 0x1205f, 0x1ff },
{ 0x1215f, 0x1ff },
{ 0x1305f, 0x1ff },
{ 0x1315f, 0x1ff },
{ 0x11005f, 0x1ff },
{ 0x11015f, 0x1ff },
{ 0x11105f, 0x1ff },
{ 0x11115f, 0x1ff },
{ 0x11205f, 0x1ff },
{ 0x11215f, 0x1ff },
{ 0x11305f, 0x1ff },
{ 0x11315f, 0x1ff },
{ 0x21005f, 0x1ff },
{ 0x21015f, 0x1ff },
{ 0x21105f, 0x1ff },
{ 0x21115f, 0x1ff },
{ 0x21205f, 0x1ff },
{ 0x21215f, 0x1ff },
{ 0x21305f, 0x1ff },
{ 0x21315f, 0x1ff },
{ 0x55, 0x1ff },
{ 0x1055, 0x1ff },
{ 0x2055, 0x1ff },
{ 0x3055, 0x1ff },
{ 0x4055, 0x1ff },
{ 0x5055, 0x1ff },
{ 0x6055, 0x1ff },
{ 0x7055, 0x1ff },
{ 0x8055, 0x1ff },
{ 0x9055, 0x1ff },
{ 0x200c5, 0x19 },
{ 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 },
{ 0x2002e, 0x2 },
{ 0x12002e, 0x2 },
{ 0x22002e, 0x2 },
{ 0x90204, 0x0 },
{ 0x190204, 0x0 },
{ 0x290204, 0x0 },
{ 0x20024, 0x1a3 },
{ 0x2003a, 0x2 },
{ 0x120024, 0x1a3 },
{ 0x2003a, 0x2 },
{ 0x220024, 0x1a3 },
{ 0x2003a, 0x2 },
{ 0x20056, 0x3 },
{ 0x120056, 0x3 },
{ 0x220056, 0x3 },
{ 0x1004d, 0xe00 },
{ 0x1014d, 0xe00 },
{ 0x1104d, 0xe00 },
{ 0x1114d, 0xe00 },
{ 0x1204d, 0xe00 },
{ 0x1214d, 0xe00 },
{ 0x1304d, 0xe00 },
{ 0x1314d, 0xe00 },
{ 0x11004d, 0xe00 },
{ 0x11014d, 0xe00 },
{ 0x11104d, 0xe00 },
{ 0x11114d, 0xe00 },
{ 0x11204d, 0xe00 },
{ 0x11214d, 0xe00 },
{ 0x11304d, 0xe00 },
{ 0x11314d, 0xe00 },
{ 0x21004d, 0xe00 },
{ 0x21014d, 0xe00 },
{ 0x21104d, 0xe00 },
{ 0x21114d, 0xe00 },
{ 0x21204d, 0xe00 },
{ 0x21214d, 0xe00 },
{ 0x21304d, 0xe00 },
{ 0x21314d, 0xe00 },
{ 0x10049, 0xeba },
{ 0x10149, 0xeba },
{ 0x11049, 0xeba },
{ 0x11149, 0xeba },
{ 0x12049, 0xeba },
{ 0x12149, 0xeba },
{ 0x13049, 0xeba },
{ 0x13149, 0xeba },
{ 0x110049, 0xeba },
{ 0x110149, 0xeba },
{ 0x111049, 0xeba },
{ 0x111149, 0xeba },
{ 0x112049, 0xeba },
{ 0x112149, 0xeba },
{ 0x113049, 0xeba },
{ 0x113149, 0xeba },
{ 0x210049, 0xeba },
{ 0x210149, 0xeba },
{ 0x211049, 0xeba },
{ 0x211149, 0xeba },
{ 0x212049, 0xeba },
{ 0x212149, 0xeba },
{ 0x213049, 0xeba },
{ 0x213149, 0xeba },
{ 0x43, 0x63 },
{ 0x1043, 0x63 },
{ 0x2043, 0x63 },
{ 0x3043, 0x63 },
{ 0x4043, 0x63 },
{ 0x5043, 0x63 },
{ 0x6043, 0x63 },
{ 0x7043, 0x63 },
{ 0x8043, 0x63 },
{ 0x9043, 0x63 },
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
{ 0x20008, 0x2ee },
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
{ 0x200b2, 0x104 },
{ 0x10043, 0x5a1 },
{ 0x10143, 0x5a1 },
{ 0x11043, 0x5a1 },
{ 0x11143, 0x5a1 },
{ 0x12043, 0x5a1 },
{ 0x12143, 0x5a1 },
{ 0x13043, 0x5a1 },
{ 0x13143, 0x5a1 },
{ 0x1200b2, 0x104 },
{ 0x110043, 0x5a1 },
{ 0x110143, 0x5a1 },
{ 0x111043, 0x5a1 },
{ 0x111143, 0x5a1 },
{ 0x112043, 0x5a1 },
{ 0x112143, 0x5a1 },
{ 0x113043, 0x5a1 },
{ 0x113143, 0x5a1 },
{ 0x2200b2, 0x104 },
{ 0x210043, 0x5a1 },
{ 0x210143, 0x5a1 },
{ 0x211043, 0x5a1 },
{ 0x211143, 0x5a1 },
{ 0x212043, 0x5a1 },
{ 0x212143, 0x5a1 },
{ 0x213043, 0x5a1 },
{ 0x213143, 0x5a1 },
{ 0x200fa, 0x1 },
{ 0x1200fa, 0x1 },
{ 0x2200fa, 0x1 },
{ 0x20019, 0x1 },
{ 0x120019, 0x1 },
{ 0x220019, 0x1 },
{ 0x200f0, 0x660 },
{ 0x200f1, 0x0 },
{ 0x200f2, 0x4444 },
{ 0x200f3, 0x8888 },
{ 0x200f4, 0x5665 },
{ 0x200f5, 0x0 },
{ 0x200f6, 0x0 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
{ 0x2002d, 0x0 },
{ 0x12002d, 0x0 },
{ 0x22002d, 0x0 },
{ 0x2007d, 0x212 },
{ 0x12007d, 0x212 },
{ 0x22007d, 0x212 },
{ 0x2007c, 0x61 },
{ 0x12007c, 0x61 },
{ 0x22007c, 0x61 },
{ 0x1004a, 0x500 },
{ 0x1104a, 0x500 },
{ 0x1204a, 0x500 },
{ 0x1304a, 0x500 },
{ 0x2002c, 0x0 },
};
/* P0 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = {
{ 0xd0000, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x54008, 0x131f },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, 0x31 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, 0x31 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0xd400 },
{ 0x54033, 0x312d },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xd400 },
{ 0x54039, 0x312d },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
{ 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
/* P1 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp1_cfg_1gb_single_die[] = {
{ 0xd0000, 0x0 },
{ 0x54002, 0x101 },
{ 0x54003, 0x190 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x84 },
{ 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
{ 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
{ 0x54033, 0x3300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
{ 0x54039, 0x3300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
{ 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
/* P2 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp2_cfg_1gb_single_die[] = {
{ 0xd0000, 0x0 },
{ 0x54002, 0x102 },
{ 0x54003, 0x64 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54012, 0x110 },
{ 0x54019, 0x84 },
{ 0x5401a, 0x33 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
{ 0x54020, 0x33 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0x8400 },
{ 0x54033, 0x3300 },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0x8400 },
{ 0x54039, 0x3300 },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
{ 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
/* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = {
{ 0xd0000, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x14 },
{ 0x54008, 0x61 },
{ 0x54009, 0xc8 },
{ 0x5400b, 0x2 },
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
{ 0x54012, 0x110 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, 0x31 },
{ 0x5401b, 0x4866 },
{ 0x5401c, 0x4800 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, 0x31 },
{ 0x54021, 0x4866 },
{ 0x54022, 0x4800 },
{ 0x54024, 0x16 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
{ 0x54032, 0xd400 },
{ 0x54033, 0x312d },
{ 0x54034, 0x6600 },
{ 0x54035, 0x48 },
{ 0x54036, 0x48 },
{ 0x54037, 0x1600 },
{ 0x54038, 0xd400 },
{ 0x54039, 0x312d },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
{ 0x5403d, 0x1600 },
{ 0xd0000, 0x1 },
};
struct dram_fsp_msg ddr_dram_fsp_msg_1gb_single_die[] = {
{
/* P0 3000mts 1D */
.drate = 3000,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg_1gb_single_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg_1gb_single_die),
},
{
/* P1 400mts 1D */
.drate = 400,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp1_cfg_1gb_single_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg_1gb_single_die),
},
{
/* P2 100mts 1D */
.drate = 100,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp2_cfg_1gb_single_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg_1gb_single_die),
},
{
/* P0 3000mts 2D */
.drate = 3000,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg_1gb_single_die,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg_1gb_single_die),
},
};
/* ddr timing config params */
struct dram_timing_info dram_timing_1gb_single_die = {
.ddrc_cfg = ddr_ddrc_cfg_1gb_single_die,
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_1gb_single_die),
.ddrphy_cfg = ddr_ddrphy_cfg_1gb_single_die,
.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg_1gb_single_die),
.fsp_msg = ddr_dram_fsp_msg_1gb_single_die,
.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg_1gb_single_die),
.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 3000, 400, 100, },
};
/*
* Generated code from MX8M_DDR_tool v3.30 using MX8M Plus RPAv7
* - 4GiB: imx8mp-gw7401 1x Micron MT53D1024M32D4DT 2-ch dual-die per channel

46
board/gateworks/venice/spl.c
View File

@ -71,6 +71,9 @@ static void spl_dram_init(int size)
dram_timing = &dram_timing_2gb_dual_die;
size = 2048;
#elif CONFIG_IMX8MP
case 1024:
dram_timing = &dram_timing_1gb_single_die;
break;
case 4096:
dram_timing = &dram_timing_4gb_dual_die;
break;
@ -83,9 +86,12 @@ static void spl_dram_init(int size)
printf("DRAM : LPDDR4 ");
if (size > 512)
printf("%d GiB\n", size / 1024);
printf("%d GiB", size / 1024);
else
printf("%d MiB\n", size);
printf("%d MiB", size);
printf(" %dMT/s %dMHz\n",
dram_timing->fsp_msg[0].drate,
dram_timing->fsp_msg[0].drate / 2);
ddr_init(dram_timing);
}
@ -121,7 +127,8 @@ static int power_init_board(void)
if ((!strncmp(model, "GW71", 4)) ||
(!strncmp(model, "GW72", 4)) ||
(!strncmp(model, "GW73", 4))) {
(!strncmp(model, "GW73", 4)) ||
(!strncmp(model, "GW7905", 6))) {
ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
if (ret) {
printf("PMIC : failed I2C1 probe: %d\n", ret);
@ -132,11 +139,22 @@ static int power_init_board(void)
printf("PMIC : failed probe: %d\n", ret);
return ret;
}
puts("PMIC : MP5416\n");
#ifdef CONFIG_IMX8MM
puts("PMIC : MP5416 (IMX8MM)\n");
/* set VDD_ARM SW3 to 0.92V for 1.6GHz */
dm_i2c_reg_write(dev, MP5416_VSET_SW3,
BIT(7) | MP5416_VSET_SW3_SVAL(920000));
#elif CONFIG_IMX8MP
puts("PMIC : MP5416 (IMX8MP)\n");
/* set VDD_ARM SW3 to 0.95V for 1.6GHz */
dm_i2c_reg_write(dev, MP5416_VSET_SW3,
BIT(7) | MP5416_VSET_SW3_SVAL(950000));
/* set VDD_SOC SW1 to 0.95V for 1.6GHz */
dm_i2c_reg_write(dev, MP5416_VSET_SW1,
BIT(7) | MP5416_VSET_SW1_SVAL(950000));
#endif
}
else if (!strncmp(model, "GW74", 4)) {
@ -327,6 +345,21 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
}
}
unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect)
{
if (!IS_SD(mmc)) {
switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
case 1:
case 2:
if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP))
raw_sect -= 32 * 2;
break;
}
}
return raw_sect;
}
const char *spl_board_loader_name(u32 boot_device)
{
switch (boot_device) {
@ -340,3 +373,8 @@ const char *spl_board_loader_name(u32 boot_device)
return NULL;
}
}
void spl_board_init(void)
{
arch_misc_init();
}

89
board/gateworks/venice/venice.c
View File

@ -6,9 +6,12 @@
#include <fdt_support.h>
#include <init.h>
#include <led.h>
#include <mmc.h>
#include <miiphy.h>
#include <mmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include "eeprom.h"
@ -17,7 +20,7 @@ int board_phys_sdram_size(phys_size_t *size)
if (!size)
return -EINVAL;
*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
*size = get_ram_size((void *)PHYS_SDRAM, (long)PHYS_SDRAM_SIZE + (long)PHYS_SDRAM_2_SIZE);
return 0;
}
@ -93,10 +96,12 @@ int board_init(void)
int board_late_init(void)
{
const char *str;
struct mmc *mmc = NULL;
char env[32];
int ret, i;
u8 enetaddr[6];
char fdt[64];
int bootdev;
/* Set board serial/model */
if (!env_get("serial#"))
@ -131,6 +136,74 @@ int board_late_init(void)
i++;
} while (!ret);
/*
* set bootdev/bootblk/bootpart (used in firmware_update script)
* dynamically depending on boot device and SoC
*/
bootdev = -1;
switch (get_boot_device()) {
case SD1_BOOT:
case MMC1_BOOT: /* SDHC1 */
bootdev = 0;
break;
case SD2_BOOT:
case MMC2_BOOT: /* SDHC2 */
bootdev = 1;
break;
case SD3_BOOT:
case MMC3_BOOT: /* SDHC3 */
bootdev = 2;
break;
default:
bootdev = 2; /* assume SDHC3 (eMMC) if booting over SDP */
break;
}
if (bootdev != -1)
mmc = find_mmc_device(bootdev);
if (mmc) {
int bootblk;
if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP))
bootblk = 32 * SZ_1K / 512;
else
bootblk = 33 * SZ_1K / 512;
mmc_init(mmc);
if (!IS_SD(mmc)) {
int bootpart;
switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
case 1: /* boot0 */
bootpart = 1;
break;
case 2: /* boot1 */
bootpart = 2;
break;
case 7: /* user */
default:
bootpart = 0;
break;
}
/* IMX8MP/IMX8MN BOOTROM v2 uses offset=0 for boot parts */
if ((IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) &&
(bootpart == 1 || bootpart == 2))
bootblk = 0;
env_set_hex("bootpart", bootpart);
env_set_hex("bootblk", bootblk);
} else { /* SD */
env_set("bootpart", "");
env_set_hex("bootblk", bootblk);
}
env_set_hex("dev", bootdev);
}
/* override soc=imx8m to provide a more specific soc name */
if (IS_ENABLED(CONFIG_IMX8MN))
env_set("soc", "imx8mn");
else if (IS_ENABLED(CONFIG_IMX8MP))
env_set("soc", "imx8mp");
else if (IS_ENABLED(CONFIG_IMX8MM))
env_set("soc", "imx8mm");
return 0;
}
@ -139,6 +212,20 @@ int board_mmc_get_env_dev(int devno)
return devno;
}
uint mmc_get_env_part(struct mmc *mmc)
{
if (!IS_SD(mmc)) {
switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
case 1:
return 1;
case 2:
return 2;
}
}
return 0;
}
int ft_board_setup(void *fdt, struct bd_info *bd)
{
const char *base_model = eeprom_get_baseboard_model();

7
board/gateworks/venice/venice.env
View File

@ -8,11 +8,11 @@ bootm_size=0x10000000
dev=2
preboot=gsc wd-disable
console=ttymxc1,115200
update_firmware=tftpboot $loadaddr $image &&
update_firmware=tftpboot $loadaddr $dir/venice-$soc-flash.bin &&
setexpr blkcnt $filesize + 0x1ff &&
setexpr blkcnt $blkcnt / 0x200 &&
mmc dev $dev &&
mmc write $loadaddr $splblk $blkcnt
mmc dev $dev $bootpart &&
mmc write $loadaddr $bootblk $blkcnt
loadfdt=if $fsload $fdt_addr_r $dir/$fdt_file1;
then echo loaded $fdt_file1;
elif $fsload $fdt_addr_r $dir/$fdt_file2;
@ -31,4 +31,3 @@ update_rootfs=tftpboot $loadaddr $image &&
gzwrite mmc $dev $loadaddr $filesize 100000 1000000
update_all=tftpboot $loadaddr $image &&
gzwrite mmc $dev $loadaddr $filesize
erase_env=mmc dev $dev; mmc erase 0x7f08 0x40

2
board/kontron/sl-mx8mm/sl-mx8mm.c
View File

@ -37,7 +37,7 @@ struct efi_capsule_update_info update_info = {
int board_phys_sdram_size(phys_size_t *size)
{
u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR);
u32 ddr_size = readl(MCU_BOOTROM_BASE_ADDR);
if (ddr_size == 4) {
*size = 0x100000000;

2
board/kontron/sl-mx8mm/spl.c
View File

@ -106,7 +106,7 @@ static void spl_dram_init(void)
}
gd->ram_size = size;
writel(size, M4_BOOTROM_BASE_ADDR);
writel(size, MCU_BOOTROM_BASE_ADDR);
}
int do_board_detect(void)

18
board/liebherr/xea/xea.c
View File

@ -62,6 +62,7 @@ static void init_clocks(void)
void board_init_f(ulong arg)
{
init_clocks();
spl_early_init();
preloader_console_init();
}
@ -203,5 +204,22 @@ int ft_board_setup(void *blob, struct bd_info *bd)
return 0;
}
#endif
/*
* NOTE:
*
* IMX28 clock "stub" DM driver!
*
* Only used for SPL stage, which is NOT using DM; serial and
* eMMC configuration.
*/
static const struct udevice_id imx28_clk_ids[] = {
{ .compatible = "fsl,imx28-clkctrl", },
{ }
};
U_BOOT_DRIVER(fsl_imx28_clkctrl) = {
.name = "fsl_imx28_clkctrl",
.id = UCLASS_CLK,
.of_match = imx28_clk_ids,
};
#endif /* CONFIG_SPL_BUILD */

1486
board/phytec/phycore_imx8mm/lpddr4_timing.c
View File

File diff suppressed because it is too large Load Diff

12
board/siemens/capricorn/board.c
View File

@ -147,7 +147,7 @@ static void enet_device_phy_reset(void)
int setup_gpr_fec(void)
{
sc_ipc_t ipc_handle = -1;
sc_err_t err = 0;
int err = 0;
unsigned int test;
/*
@ -175,35 +175,35 @@ int setup_gpr_fec(void)
*/
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, 1);
if (err != SC_ERR_NONE)
if (err)
printf("Error in setting up SC_C %d\n\r", SC_C_TXCLK);
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
debug("TEST SC_C %d-->%d\n\r", SC_C_TXCLK, test);
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, 0);
if (err != SC_ERR_NONE)
if (err)
printf("Error in setting up SC_C %d\n\r", SC_C_CLKDIV);
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, &test);
debug("TEST SC_C %d-->%d\n\r", SC_C_CLKDIV, test);
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_50, 0);
if (err != SC_ERR_NONE)
if (err)
printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_50);
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_50, test);
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_125, 1);
if (err != SC_ERR_NONE)
if (err)
printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_125);
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_125, test);
err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, 1);
if (err != SC_ERR_NONE)
if (err)
printf("Error in setting up SC_C %d\n\r", SC_C_SEL_125);
sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, &test);

2
board/technexion/pico-imx8mq/pico-imx8mq.c
View File

@ -54,7 +54,7 @@ int board_early_init_f(void)
int board_phys_sdram_size(phys_size_t *size)
{
int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
int ddr_size = readl(MCU_BOOTROM_BASE_ADDR);
if (ddr_size == 0x4) {
*size = 0x100000000;

2
board/technexion/pico-imx8mq/spl.c
View File

@ -89,7 +89,7 @@ static void spl_dram_init(void)
printf("%s: LPDDR4 %d GiB\n", __func__, size);
ddr_init(dram_timing);
writel(size, M4_BOOTROM_BASE_ADDR);
writel(size, MCU_BOOTROM_BASE_ADDR);
}
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)

10
board/toradex/apalis-imx8/apalis-imx8.c
View File

@ -85,18 +85,18 @@ static void setup_iomux_uart(void)
static uint32_t do_get_tdx_user_fuse(int a, int b)
{
sc_err_t sciErr;
int sciErr;
u32 val_a = 0;
u32 val_b = 0;
sciErr = sc_misc_otp_fuse_read(-1, a, &val_a);
if (sciErr != SC_ERR_NONE) {
if (sciErr) {
printf("Error reading out user fuse %d\n", a);
return 0;
}
sciErr = sc_misc_otp_fuse_read(-1, b, &val_b);
if (sciErr != SC_ERR_NONE) {
if (sciErr) {
printf("Error reading out user fuse %d\n", b);
return 0;
}
@ -131,9 +131,9 @@ void board_mem_get_layout(u64 *phys_sdram_1_start,
{
u32 is_quadplus = 0, val = 0;
struct tdx_user_fuses tdxramfuses;
sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
int scierr = sc_misc_otp_fuse_read(-1, 6, &val);
if (scierr == SC_ERR_NONE) {
if (scierr) {
/* QP has one A72 core disabled */
is_quadplus = ((val >> 4) & 0x3) != 0x0;
}

20
board/toradex/colibri-imx8x/colibri-imx8x.c
View File

@ -12,6 +12,7 @@
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
#include <firmware/imx/sci/sci.h>
#include <asm/arch/snvs_security_sc.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/io.h>
@ -43,9 +44,9 @@ static void setup_iomux_uart(void)
static int is_imx8dx(void)
{
u32 val = 0;
sc_err_t sc_err = sc_misc_otp_fuse_read(-1, 6, &val);
int sc_err = sc_misc_otp_fuse_read(-1, 6, &val);
if (sc_err == SC_ERR_NONE) {
if (sc_err) {
/* DX has two A35 cores disabled */
return (val & 0xf) != 0x0;
}
@ -70,7 +71,7 @@ void board_mem_get_layout(u64 *phys_sdram_1_start,
int board_early_init_f(void)
{
sc_pm_clock_rate_t rate;
sc_err_t err = 0;
int err;
/*
* This works around that having only UART3 up the baudrate is 1.2M
@ -78,13 +79,13 @@ int board_early_init_f(void)
*/
rate = 80000000;
err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
if (err != SC_ERR_NONE)
if (err)
return 0;
/* Set UART3 clock root to 80 MHz and enable it */
rate = SC_80MHZ;
err = sc_pm_setup_uart(SC_R_UART_3, rate);
if (err != SC_ERR_NONE)
if (err)
return 0;
setup_iomux_uart();
@ -139,6 +140,13 @@ int board_init(void)
{
board_gpio_init();
if (IS_ENABLED(CONFIG_IMX_SNVS_SEC_SC_AUTO)) {
int ret = snvs_security_sc_init();
if (ret)
return ret;
}
return 0;
}
@ -170,6 +178,8 @@ int board_late_init(void)
env_set("board_rev", "v1.0");
#endif
build_info();
select_dt_from_module_version();
return 0;

6
board/toradex/colibri_imx6/colibri_imx6.c
View File

@ -767,8 +767,7 @@ MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
/*
* MDMISC mirroring interleaved (row/bank/col)
*/
/* TODO: check what the RALAT field does */
MX6_MMDC_P0_MDMISC, 0x00081740,
MX6_MMDC_P0_MDMISC, 0x000b17c0,
/*
* MDSCR con_req
@ -900,8 +899,7 @@ MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
/*
* MDMISC mirroring interleaved (row/bank/col)
*/
/* TODO: check what the RALAT field does */
MX6_MMDC_P0_MDMISC, 0x00081740,
MX6_MMDC_P0_MDMISC, 0x000b17c0,
/*
* MDSCR con_req

1
board/toradex/common/tdx-cfg-block.c
View File

@ -139,6 +139,7 @@ const struct toradex_som toradex_modules[] = {
[66] = { "Verdin iMX8M Plus Quad 8GB WB", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
[67] = { "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) },
[68] = { "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) },
[70] = { "Verdin iMX8M Plus Quad 8GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) },
};
const char * const toradex_carrier_boards[] = {

2
board/toradex/common/tdx-cfg-block.h
View File

@ -94,6 +94,8 @@ enum {
VERDIN_IMX8MPQ_8GB_WIFI_BT,
APALIS_IMX8QM_8GB_WIFI_BT_IT,
VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN,
/* 69 */
VERDIN_IMX8MPQ_8GB_WIFI_BT_IT = 70, /* 70 */
};
enum {

1
board/toradex/verdin-imx8mm/MAINTAINERS
View File

@ -3,7 +3,6 @@ M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini
S: Maintained
F: arch/arm/dts/imx8mm-verdin.dtsi
F: arch/arm/dts/imx8mm-verdin-dahlia.dtsi
F: arch/arm/dts/imx8mm-verdin-dev.dtsi
F: arch/arm/dts/imx8mm-verdin-wifi.dtsi
F: arch/arm/dts/imx8mm-verdin-wifi-dev.dts

1
board/toradex/verdin-imx8mp/MAINTAINERS
View File

@ -1,6 +1,5 @@
Verdin iMX8M Plus
F: arch/arm/dts/imx8mp-verdin.dtsi
F: arch/arm/dts/imx8mp-verdin-dahlia.dtsi
F: arch/arm/dts/imx8mp-verdin-dev.dtsi
F: arch/arm/dts/imx8mp-verdin-wifi.dtsi
F: arch/arm/dts/imx8mp-verdin-wifi-dev.dts

3
board/toradex/verdin-imx8mp/verdin-imx8mp.c
View File

@ -81,7 +81,8 @@ static void select_dt_from_module_version(void)
*/
is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_WIFI_BT_IT) ||
(tdx_hw_tag.prodid == VERDIN_IMX8MPQ_2GB_WIFI_BT_IT) ||
(tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT);
(tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT) ||
(tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT_IT);
}
if (is_wifi)

214
board/variscite/imx8mn_var_som/imx8mn_var_som.c
View File

@ -1,11 +1,50 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
* Copyright 2018-2020 Variscite Ltd.
* Copyright 2023 DimOnOff Inc.
*/
#include <common.h>
#include <dm.h>
#include <env.h>
#include <fdtdec.h>
#include <fdt_support.h>
#include <i2c_eeprom.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/global_data.h>
#include <dt-bindings/gpio/gpio.h>
#include <linux/libfdt.h>
DECLARE_GLOBAL_DATA_PTR;
/* Optional SOM features flags. */
#define VAR_EEPROM_F_WIFI BIT(0)
#define VAR_EEPROM_F_ETH BIT(1) /* Ethernet PHY on SOM. */
#define VAR_EEPROM_F_AUDIO BIT(2)
#define VAR_EEPROM_F_MX8M_LVDS BIT(3) /* i.MX8MM, i.MX8MN, i.MX8MQ only */
#define VAR_EEPROM_F_MX8Q_SOC_ID BIT(3) /* 0 = i.MX8QM, 1 = i.MX8QP */
#define VAR_EEPROM_F_NAND BIT(4)
#define VAR_IMX8_EEPROM_MAGIC 0x384D /* "8M" */
/* Number of DRAM adjustment tables. */
#define DRAM_TABLES_NUM 7
struct var_imx8_eeprom_info {
u16 magic;
u8 partnumber[3]; /* Part number */
u8 assembly[10]; /* Assembly number */
u8 date[9]; /* Build date */
u8 mac[6]; /* MAC address */
u8 somrev;
u8 eeprom_version;
u8 features; /* SOM features */
u8 dramsize; /* DRAM size */
u8 off[DRAM_TABLES_NUM + 1]; /* DRAM table offsets */
u8 partnumber2[5]; /* Part number 2 */
} __packed;
static void setup_fec(void)
{
@ -28,3 +67,178 @@ int board_mmc_get_env_dev(int devno)
{
return devno;
}
#if !defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_DISPLAY_BOARDINFO)
static void display_som_infos(struct var_imx8_eeprom_info *info)
{
char partnumber[sizeof(info->partnumber) +
sizeof(info->partnumber2) + 1];
char assembly[sizeof(info->assembly) + 1];
char date[sizeof(info->date) + 1];
/* Read first part of P/N. */
memcpy(partnumber, info->partnumber, sizeof(info->partnumber));
/* Read second part of P/N. */
if (info->eeprom_version >= 3)
memcpy(partnumber + sizeof(info->partnumber), info->partnumber2,
sizeof(info->partnumber2));
memcpy(assembly, info->assembly, sizeof(info->assembly));
memcpy(date, info->date, sizeof(info->date));
/* Make sure strings are null terminated. */
partnumber[sizeof(partnumber) - 1] = '\0';
assembly[sizeof(assembly) - 1] = '\0';
date[sizeof(date) - 1] = '\0';
printf("SOM board: P/N: %s, Assy: %s, Date: %s\n"
" Wifi: %s, EthPhy: %s, Rev: %d\n",
partnumber, assembly, date,
info->features & VAR_EEPROM_F_WIFI ? "yes" : "no",
info->features & VAR_EEPROM_F_ETH ? "yes" : "no",
info->somrev);
}
static int var_read_som_eeprom(struct var_imx8_eeprom_info *info)
{
const char *path = "eeprom-som";
struct udevice *dev;
int ret, off;
off = fdt_path_offset(gd->fdt_blob, path);
if (off < 0) {
pr_err("%s: fdt_path_offset() failed: %d\n", __func__, off);
return off;
}
ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
if (ret) {
pr_err("%s: uclass_get_device_by_of_offset() failed: %d\n",
__func__, ret);
return ret;
}
ret = i2c_eeprom_read(dev, 0, (uint8_t *)info,
sizeof(struct var_imx8_eeprom_info));
if (ret) {
pr_err("%s: i2c_eeprom_read() failed: %d\n", __func__, ret);
return ret;
}
if (htons(info->magic) != VAR_IMX8_EEPROM_MAGIC) {
/* Do not fail if the content is invalid */
pr_err("Board: Invalid board info magic: 0x%08x, expected 0x%08x\n",
htons(info->magic), VAR_IMX8_EEPROM_MAGIC);
}
return 0;
}
int checkboard(void)
{
int rc;
struct var_imx8_eeprom_info *info;
info = malloc(sizeof(struct var_imx8_eeprom_info));
if (!info)
return -ENOMEM;
rc = var_read_som_eeprom(info);
if (rc)
return rc;
display_som_infos(info);
#if defined(CONFIG_BOARD_TYPES)
gd->board_type = info->features;
#endif /* CONFIG_BOARD_TYPES */
return 0;
}
#endif /* CONFIG_DISPLAY_BOARDINFO */
static int insert_gpios_prop(void *blob, int node, const char *prop,
unsigned int phandle, u32 gpio, u32 flags)
{
fdt32_t val[3] = { cpu_to_fdt32(phandle), cpu_to_fdt32(gpio),
cpu_to_fdt32(flags) };
return fdt_setprop(blob, node, prop, &val, sizeof(val));
}
static int configure_phy_reset_gpios(void *blob)
{
int node;
int phynode;
int ret;
u32 handle;
u32 gpio;
u32 flags;
char path[1024];
const char *eth_alias = "ethernet0";
snprintf(path, sizeof(path), "%s/mdio/ethernet-phy@4",
fdt_get_alias(blob, eth_alias));
phynode = fdt_path_offset(blob, path);
if (phynode < 0) {
pr_err("%s(): unable to locate PHY node: %s\n", __func__, path);
return 0;
}
if (gd_board_type() & VAR_EEPROM_F_ETH) {
snprintf(path, sizeof(path), "%s",
fdt_get_alias(blob, "gpio0")); /* Alias to gpio1 */
gpio = 9;
flags = GPIO_ACTIVE_LOW;
} else {
snprintf(path, sizeof(path), "%s/gpio@20",
fdt_get_alias(blob, "i2c1")); /* Alias to i2c2 */
gpio = 5;
flags = GPIO_ACTIVE_HIGH;
}
node = fdt_path_offset(blob, path);
if (node < 0) {
pr_err("%s(): unable to locate GPIO node: %s\n", __func__,
path);
return 0;
}
handle = fdt_get_phandle(blob, node);
if (handle < 0) {
pr_err("%s(): unable to locate GPIO controller handle: %s\n",
__func__, path);
}
ret = insert_gpios_prop(blob, phynode, "reset-gpios",
handle, gpio, flags);
if (ret < 0) {
pr_err("%s(): failed to set reset-gpios property\n", __func__);
return ret;
}
return 0;
}
#if defined(CONFIG_OF_BOARD_FIXUP)
int board_fix_fdt(void *blob)
{
/* Fix U-Boot device tree: */
return configure_phy_reset_gpios(blob);
}
#endif /* CONFIG_OF_BOARD_FIXUP */
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
/* Fix kernel device tree: */
return configure_phy_reset_gpios(blob);
}
#endif /* CONFIG_OF_BOARD_SETUP */
#endif /* CONFIG_SPL_BUILD */

11
configs/imx28_xea_defconfig
View File

@ -14,6 +14,9 @@ CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="imx28-xea"
CONFIG_SPL_TEXT_BASE=0x1000
CONFIG_TARGET_XEA=y
CONFIG_SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT=y
CONFIG_SPL_MXS_PMU_DISABLE_BATT_CHARGE=y
# CONFIG_SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR is not set
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_STACK=0x20000
@ -26,6 +29,8 @@ CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_FIT=y
CONFIG_TIMESTAMP=y
# CONFIG_BOOTMETH_EXTLINUX is not set
# CONFIG_BOOTMETH_VBE is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8"
@ -95,7 +100,7 @@ CONFIG_MMC_MXS=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_ISSI=y
CONFIG_SPI_FLASH_SPANSION=y
@ -113,9 +118,9 @@ CONFIG_PINCTRL_MXS=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CONS_INDEX=0
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXS_SPI=y
CONFIG_FS_FAT=y
# CONFIG_SPL_OF_LIBFDT is not set

2
configs/imx28_xea_sb_defconfig
View File

@ -94,7 +94,9 @@ CONFIG_PINCTRL_MXS=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=0
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXS_SPI=y

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