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watchdog: add sl28cpld watchdog driver
The watchdog timer is part of the sl28cpld management controller. The watchdog timer usually supervises the bootloader boot-up and if it bites the failsafe bootloader will be activated. Apart from that it supports the usual board level reset and one SMARC speciality: driving the WDT_TIMEOUT# signal. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Michael Walle
Priyanka Jain
parent
42595eb706
commit
f606c9a895
@ -1165,6 +1165,7 @@ SL28CLPD
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M: Michael Walle <michael@walle.cc>
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S: Maintained
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F: drivers/misc/sl28cpld.c
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F: drivers/watchdog/sl28cpld-wdt.c
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SPI
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M: Jagan Teki <jagan@amarulasolutions.com>
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@ -35,23 +35,6 @@ The board is fully failsafe, you can't break anything. But because you've
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disabled the builtin watchdog you might have to manually enter failsafe
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mode by asserting the ``FORCE_RECOV#`` line during board reset.
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Disable the builtin watchdog
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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- boot into the failsafe bootloader, either by asserting the
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``FORCE_RECOV#`` line or if you still have the original bootloader
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installed you can use the command::
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> wdt dev cpld_watchdog@4a; wdt expire 1
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- in the failsafe bootloader use the "sl28 nvm" command to disable
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the automatic start of the builtin watchdog::
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> sl28 nvm 0008
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- power-cycle the board
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Update image
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------------
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@ -82,6 +65,42 @@ u-boot (yet). But you can use the i2c command to access it.
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> i2c md 4a 3.1 1
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Builtin watchdog
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----------------
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The builtin watchdog will supervise the bootloader startup. If anything
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goes wrong it will reset the board and boot into the failsafe bootloader.
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Once the bootloader is started successfully, it will disable the watchdog
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timer.
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wdt command flags
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^^^^^^^^^^^^^^^^^
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The `wdt start` as well as the `wdt expire` command take a flags argument.
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The supported bitmask is as follows.
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| Bit | Description |
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| --- | ----------------------------- |
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| 0 | Enable failsafe mode |
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| 1 | Lock the control register |
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| 2 | Disable board reset |
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| 3 | Enable WDT_TIME_OUT# line |
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For example, you can use `wdt expire 1` to issue a reset and boot into the
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failsafe bootloader.
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Disable the builtin watchdog
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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If for some reason, this isn't a desired behavior, the watchdog can also
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be configured to not be enabled on board reset. It's configuration is saved
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in the non-volatile board configuration bits. To change these you can use
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the `sl28 nvm` command.
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For more information on the non-volatile board configuration bits, see the
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following section.
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Non-volatile Board Configuration Bits
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-------------------------------------
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@ -266,6 +266,13 @@ config WDT_SBSA
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In the single stage mode, when the timeout is reached, your system
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will be reset by WS1. The first signal (WS0) is ignored.
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config WDT_SL28CPLD
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bool "sl28cpld watchdog timer support"
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depends on WDT && SL28CPLD
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help
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Enable support for the watchdog timer in the Kontron sl28cpld
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management controller.
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config WDT_SP805
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bool "SP805 watchdog timer support"
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depends on WDT
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@ -35,6 +35,7 @@ obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o
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obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
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obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
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obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
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obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o
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obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
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obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
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obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o
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109
drivers/watchdog/sl28cpld-wdt.c
Normal file
109
drivers/watchdog/sl28cpld-wdt.c
Normal file
@ -0,0 +1,109 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Watchdog driver for the sl28cpld
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*
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* Copyright (c) 2021 Michael Walle <michael@walle.cc>
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*/
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#include <common.h>
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#include <dm.h>
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#include <wdt.h>
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#include <sl28cpld.h>
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#include <div64.h>
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#define SL28CPLD_WDT_CTRL 0x00
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#define WDT_CTRL_EN0 BIT(0)
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#define WDT_CTRL_EN1 BIT(1)
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#define WDT_CTRL_EN_MASK GENMASK(1, 0)
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#define WDT_CTRL_LOCK BIT(2)
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#define WDT_CTRL_ASSERT_SYS_RESET BIT(6)
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#define WDT_CTRL_ASSERT_WDT_TIMEOUT BIT(7)
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#define SL28CPLD_WDT_TIMEOUT 0x01
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#define SL28CPLD_WDT_KICK 0x02
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#define WDT_KICK_VALUE 0x6b
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static int sl28cpld_wdt_reset(struct udevice *dev)
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{
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return sl28cpld_write(dev, SL28CPLD_WDT_KICK, WDT_KICK_VALUE);
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}
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static int sl28cpld_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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{
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int ret, val;
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val = sl28cpld_read(dev, SL28CPLD_WDT_CTRL);
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if (val < 0)
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return val;
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/* (1) disable watchdog */
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val &= ~WDT_CTRL_EN_MASK;
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ret = sl28cpld_write(dev, SL28CPLD_WDT_CTRL, val);
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if (ret)
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return ret;
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/* (2) set timeout */
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ret = sl28cpld_write(dev, SL28CPLD_WDT_TIMEOUT, lldiv(timeout, 1000));
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if (ret)
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return ret;
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/* (3) kick it, will reset timer to the timeout value */
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ret = sl28cpld_wdt_reset(dev);
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if (ret)
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return ret;
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/* (4) enable either recovery or normal one */
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if (flags & BIT(0))
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val |= WDT_CTRL_EN1;
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else
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val |= WDT_CTRL_EN0;
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if (flags & BIT(1))
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val |= WDT_CTRL_LOCK;
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if (flags & BIT(2))
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val &= ~WDT_CTRL_ASSERT_SYS_RESET;
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else
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val |= WDT_CTRL_ASSERT_SYS_RESET;
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if (flags & BIT(3))
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val |= WDT_CTRL_ASSERT_WDT_TIMEOUT;
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else
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val &= ~WDT_CTRL_ASSERT_WDT_TIMEOUT;
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return sl28cpld_write(dev, SL28CPLD_WDT_CTRL, val);
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}
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static int sl28cpld_wdt_stop(struct udevice *dev)
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{
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int val;
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val = sl28cpld_read(dev, SL28CPLD_WDT_CTRL);
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if (val < 0)
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return val;
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return sl28cpld_write(dev, SL28CPLD_WDT_CTRL, val & ~WDT_CTRL_EN_MASK);
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}
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static int sl28cpld_wdt_expire_now(struct udevice *dev, ulong flags)
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{
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return sl28cpld_wdt_start(dev, 0, flags);
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}
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static const struct wdt_ops sl28cpld_wdt_ops = {
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.start = sl28cpld_wdt_start,
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.reset = sl28cpld_wdt_reset,
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.stop = sl28cpld_wdt_stop,
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.expire_now = sl28cpld_wdt_expire_now,
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};
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static const struct udevice_id sl28cpld_wdt_ids[] = {
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{ .compatible = "kontron,sl28cpld-wdt", },
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{}
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};
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U_BOOT_DRIVER(sl28cpld_wdt) = {
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.name = "sl28cpld-wdt",
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.id = UCLASS_WDT,
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.of_match = sl28cpld_wdt_ids,
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.ops = &sl28cpld_wdt_ops,
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};
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